Lattice Semiconductor ECP5 - Figure 7.11. DDR_MEM Clock;Address;Command Tab; Table 7.7. DDR_MEM Clock;Address;Command Parameters

ECP5 and ECP5-5G High-Speed I/O Interface
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FPGA-TN-02035-1.3 61
Figure 7.11 shows the Clock/Address/Command tab of the DDR memory Catalog.
Figure 7.11. DDR_MEM Clock/Address/Command Tab
Table 7.7 lists the values that can be used for the Clock/Address/Command settings.
Table 7.7. DDR_MEM Clock/Address/Command Parameters
User Interface Option
Range
Default Value
Number of Clocks
DDR2: 1, 2, 4
DDR3: 1, 2, 4
DDR3L: 1, 2, 4
LPDDR2: 1
LPDDR3: 1
DDR3: 1
DDR2: 1
DDR3L: 1
LPDDR2: 1
LPDDR3: 1
Address Width
DDR2: 13 – 16
DDR3: 13 – 16
DDR3L: 13 – 16
LPDDR2: Blank
LPDDR3: Blank
DDR2: 13
DDR3: 14
DDR3L: 14
LPDDR2: Blank
LPDDR3: Blank
Bank Address Width
DDR2: 2, 3
DDR3: 3
DDR3L: 3
LPDDR2: Blank
LPDDR3: Blank
DDR2: 2
DDR3: 3
DDR3L: 3
LPDDR2: Blank
LPDDR3: Blank
Number of Chip Selects
DDR2: 1, 2, 4
DDR3: 1, 2, 4
DDR3L: 1, 2, 4
LPDDR2: 1
LPDDR3: 1
DDR2: 1
DDR3: 1
DDR3L: 1
LPDDR2: 1
LPDDR3: 1
Number of Clock Enables
= Number of Chip Selects
= Number of Chip Selects
Number of ODT
DDR2, DDR3, DDR3L = Number of Chip Selects
LPDDR2: Blank
LPDDR3 = Number of Chip Selects
DDR2, DDR3, DDR3L = Number of Chip Selects
LPDDR2: Blank
LPDDR3 = Number of chip Selects