Lattice Semiconductor ECP5 - Iddrx2 F; Iddr71 B; Figure 8.6. IDDRX2 F Primitive; Figure 8.7. IDDR71 B

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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FPGA-TN-02035-1.3 69
8.8.2. IDDRX2F
This primitive is used to receive Generic DDR with 2x gearing.
Q1
SCLK
0Q
D
RST
ALIGNWD
ECLK
Q2
Q3
IDDRX2F
Figure 8.6. IDDRX2F Primitive
Table 8.10. IDDRX2F Port List
Port
I/O
Description
D
I
DDR data input
ECLK
I
Fast Edge Clock
SCLK
I
Primary Clock input (divide-by-2 of ECLK)
RST
I
Reset to DDR registers
ALIGNWD
I
This signal is used for word alignment. It shifts the word by one bit.
Q0, Q2
O
Data at positive edge of input ECLK
Q1, Q3
O
Data at negative edge of input ECLK
8.8.3. IDDR71B
This primitive is used for 7:1 LVDS input side implementation.
SCLK
Q0D
Q1
RST
ALIGNWD
ECLK
Q2
Q3
Q4
Q5
Q6
IDDR71B
Figure 8.7. IDDR71B
Table 8.11. IDDRX2F Port List
Port
I/O
Description
D
I
DDR data input
ECLK
I
Edge Clock
SCLK
I
Primary Clock (divide-by-3.5 of ECLK)
RST
I
Reset to DDR registers
ALIGNWD
I
This signal is used for word alignment. It shifts the word by one bit.
Q0 to Q6
O
7 bits of output data.