ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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FPGA-TN-02035-1.3 73
Indicates the delay counter has reached max value for the read side DQS delay.
Used to reset back to 90° delay for write side DQSW270
Pulse is required to change delay settings. The value on Direction is sampled at the falling edge
of MOVE. Used to change delay on the write side DQSW270.
Indicates delay direction. 1 decrease delay count, 0 increases the delay count. Used to change
delay on the write side DQSW270.
Indicates the delay counter has reached the maximum value for the write side DQSW270 delay.
90° delay DQS used for read
90° delay clock used for DQ write
Read pointer for IFIFO module
Write pointer for IFIFO module
Signal indicating start of valid data
Table 8.16. DQSBUFM Attributes
Sign bit for READ delay adjustment, DDR input
Value of delay for input DDR.
0–255 (PLUS)
1–256 (MINUS)
Sign bit for WRITE delay adjustment, DDR output
Value of delay for output DDR
0–255 (PLUS)
1–256 (MINUS)
*
Note: Default value is set based on device characterization to achieve the 90° phase shift.
8.11. Input and Output Memory DDR Primitives
The ECP5 and ECP5-5G device IDDR/ODDR modules support 4:1 (2x) gearing mode that are used to implement the
memory functions.
Table 8.17 shows a summary of all the DDR memory primitives. See the sections below for detailed descriptions.
Table 8.17. Summary of all DDR Memory Primitives
ODDRX2DQA
CS_N and CKE:
ODDRX2DQA*
ODDRX2DQA
CS_N, CKE and
ODT:
ODDRX2DQA1
*
Note: The D0 and D1 inputs are tied together. The D2 and D3 inputs are also tied together.
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