Lattice Semiconductor ECP5 - Memory Input DDR Primitives; Iddrx2 Dqa; Figure 8.12. IDDRX2 DQA Primitive; Table 8.18. DQSBUF Port List

ECP5 and ECP5-5G High-Speed I/O Interface
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74 FPGA-TN-02035-1.3
8.12. Memory Input DDR Primitives
The following are the primitives used to implement various memory DDR input configurations.
8.12.1. IDDRX2DQA
This primitive is used to implement the DDR2 memory input interface at higher speeds and DDR3 memory interface.
SCLK
D
Q0
Q1
RST
ECLK
Q2
Q3
IDDRX2DQA
RDPNTR[2:0]
WRPNTR[2:0]
DQSR90
QWL
Figure 8.12. IDDRX2DQA Primitive
Table 8.18. DQSBUF Port List
Port
I/O
Description
D
I
DDR data input
RST
I
Reset to DDR registers
DQSR90
I
DQS clock Input
ECLK
I
Fast Edge Clock
SCLK
I
Primary Clock input (divide-by-2 of ECLK)
RDPNTR[2:0]
I
Read pointer from the DQSBUF module used to transfer data to ECLK
WRPNTR[2:0]
I
Write pointer from the DQSBUF module used to transfer data to ECLK
Q0, Q2
O
Data at positive edge of DQS
Q1, Q3
O
Data at negative edge of DQS
QWL
O
Data output used for write leveling
Table 8.19. Memory Primitive Attributes
Attribute
Description
Values
Default
Valid Primitives
REGSET
Set the Tristate register to either SET or RESET. By Default value is
SET so that all output buffers are tristated by default
SET, RESET
SET
TSHX2DQA