Lattice Semiconductor ECP5 - Output DDR Primitives; Oddrx1 F; Oddrx2 F; Figure 8.8. ODDRX1 F

ECP5 and ECP5-5G High-Speed I/O Interface
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70 FPGA-TN-02035-1.3
8.9. Output DDR Primitives
The following are the primitives used to implement various Generic DDR output configurations.
8.9.1. ODDRX1F
This primitive is used to transmit Generic DDR with 1x gearing.
D0
D1
SCLK
RST
Q
ODDRX1F
Figure 8.8. ODDRX1F
Table 8.12. ODDRX1F Port List
Port
I/O
Description
D0, D1
I
Parallel data input to ODDR (D0 is sent out first then D1)
SCLK
I
SCLK input
RST
I
Reset input
Q
O
DDR data output on both edges of SCLK
8.9.2. ODDRX2F
This primitive is used to receive Generic DDR with 2x gearing.
D0
D1
SCLK
RST
Q
ODDRX2F
D2
D3
ECLK
Figure 8.9. ODDRX2F
Table 8.13. ODDRX2F Port List
Port
I/O
Description
D0, D1, D2, D3
I
Parallel Data input to the ODDR (D0 is sent out first and D3 last)
ECLK
I
ECLK input (2x speed of SCLK)
SCLK
I
SCLK input
RST
I
Reset input
Q
O
DDR data output on both edges of ECLK