Lattice Semiconductor ECP5 - Configuring DDR Memory Interfaces; Figure 7.9. DDR_MEM Option Selected in the Catalog Tab of Clarity Designer; Table 7.5. GDDR_7:1 LVDS Configuration Parameters

ECP5 and ECP5-5G High-Speed I/O Interface
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58 FPGA-TN-02035-1.3
Table 7.5 explains the various parameters in this tab.
Table 7.5. GDDR_7:1 LVDS Configuration Parameters
User Interface Option
Description
Values
Interface Type
Type of interface (Receive or Transmit)
Transmit, Receive
Bus Width
Bus width for 1 channel of 7:1 LVDS interface
1–16
Clock Frequency
Pixel clock speed
3.125 MHz–108 MHz
Enable Bit Alignment and Word
Alignment
Soft IP included with the module to implement
Bit and Word alignment
Enable, Disable
7.5. Configuring DDR Memory Interfaces
Clarity Designer is used to configure the PHY portion of the DDR2, DDR3, DDR3L, LPDDR2, and LPDDR3 memory
interfaces. For the detailed block diagram for each interface, see the Memory Interface Implementation section.
To build a DDR Memory interface, select DDR_MEM option under Architecture Modules – I/O in the Catalog tab of
Clarity Designer. Enter the name of the module.
Figure 7.9 shows the type of interface selected as GDDR_MEM and module name entered. This module can then be
configured by clicking the Customize button.
Figure 7.9. DDR_MEM Option Selected in the Catalog Tab of Clarity Designer