Lattice Semiconductor ECP5 - Write Implementation (DDR2, DDR3;DDR3 L Address, Command, and Clock); Figure 6.10. DDR2, DDR3;DDR3 L Address, Command, and Clock Generation

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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FPGA-TN-02035-1.3 41
This interface uses the following modules:
 ODDRX2DQA to generate the data DQ and DM signals. TSHX2DQA is used to generate the tristate control for the
DQ output.
 ODDRX2DQSB to generate DQS output. TSHX2DQSA is used to generate the DQS tristate control.
 DQSW270 which is the 270 degree delayed DQS signal is used to generate the DQ and DM outputs.
 DQSW is 90° shifted from the DQSW270 is used to generate DQS output.
 The DQSW270 and DQSW clocks are generated in the DQSBUFM module shown on the Read side Implementation
figure.
 When write leveling is enabled, the dynamic delay for write leveling (DYNDELAY[7:0]) is applied both to DQSW and
DQSW270 so that the DQ and DQS phase relationship is maintained.
 ECLK and SCLK are used inside the ODDRX2 module before data is transferred to the DQSW270 and DQSW clocks.
The ECLK is generated by the EHXPLLL module and the SCLK is generated by the CLKDIVF module, both shown in
the Read side implementation.
 Figure 6.9 shows one tristate. The software generates one tristate element for each DQ port.
6.3.3. Write Implementation (DDR2, DDR3/DDR3L Address, Command, and Clock)
DDR2, DDR3, DDR3L write side interface side to generate the clock, address, and command uses the following modules:
 ODDRX2F with inputs tied to constants to generate the DDRCLK output.
 The ADDR, BA, CASN, RASN, WEN, CKE, and ODT command and address signals are generated using the ODDRX1F.
CSN output is generated using OSHX2A.
 Both ECLK and SCLK is used in these elements. This is same ECLK and SLCK generated in the Read side.
ddrclk
D1
D2
SCLK
RST
Q
D3
D4
ECLK
1'b0
1'b1
1'b0
1'b1
SCLK
RST
Q
ECLK
_
D0
SCLK
RST
Q
ECLK
SCLK
RST
Q
DELAYG
DEL_MODE=
DQS_CMD_CLK
addr. ba
cke , odt
casn, rasn, wen
csn
DELAYG
D0
D1
SCLK
RST
Q
ECLK
casn_din(0), rasn_din(0), wen_din(0)
casn_din(1), rasn_din(1), wen_din(1)
Eclk (from ECLKSYNCA)
DDR_reset
addr_din(0), ba_din(0)
addr_din(1), ba_din(1)
Sclk (from CLKDIVD)
csn_din(0)
csn_din(1)
cke_din(0), odt_din(0)
cke_din(1), odt_din(1)
D0
D1
D1
D0
D1
ODDRX2F
ODDRX1F
ODDRX1F
ODDRX1F
OSHX2A
DEL_MODE=
DQS_CMD_CLK
Figure 6.10. DDR2, DDR3/DDR3L Address, Command, and Clock Generation