Lattice Semiconductor ECP5 - Delayf; Delayg; Figure 8.1. DELAYF Primitive; Figure 8.2. DELAYG Primitive

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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FPGA-TN-02035-1.3 65
8.2. DELAYF
By default, the DELAYF is configured to factory delay settings based on the clocking structure. You can overwrite the
DELAY setting using the MOVE and DIRECTION control inputs. The LOADN resets the delay back to the default value.
Z
A
DELAYF
LOADN
MOVE
DIRECTION
Z
CFLAG
Figure 8.1. DELAYF Primitive
Table 8.2. DELAYF Port List
Port
I/O
Description
A
I
Data input from pin or output register block
LOADN
I
0 on LOADN resets to default delay setting
MOVE
I
Pulse on MOVE changes delay setting. DIRECTION is sampled at falling edge of MOVE.
DIRECTION
I
1 to decrease delay and 0 to increase delay
Z
O
Delayed data to input register block or to pin
CFLAG
O
Flag indicating the delay counter has reached the max (when moving up) or min (when moving down) value
8.3. DELAYG
By default, the DELAYG is configured to factory delay settings based on the clocking structure. You cannot change the
delay when using this module.
ZA
DELAYG
Z
Figure 8.2. DELAYG Primitive
Table 8.3. DELAYG Port List
Port
I/O
Description
A
I
Data input from pin or output register block
Z
O
Delayed data to input register block or to pin