Lattice Semiconductor ECP5 - Mem_Sync; Bw_Align; Figure 9.3. MEM_SYNC Ports; Figure 9.4. BW_ALIGN Ports

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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80 FPGA-TN-02035-1.3
9.1.3. MEM_SYNC
This module is needed to startup external memory controller interfaces with 2x gearing.
DLL_LOCK
FREEZE
UDDCNTLN
DLL_RESET
DDR_RESET
STOP
START_CLK
RST
UPDATE
PAUSE
READY
MEM _SYNC
Figure 9.3. MEM_SYNC Ports
Table 9.5. MEM_SYNC Port Description
Port
I/O
Description
SYNC_CLK
I
Startup clock. This cannot be the RX_CLK or divided version. It can be other low speed
continuously running clock. For example, oscillator clock.
RST
I
Active high reset to this sync circuit. When RST=1, STOP=0, FREEZE=0, UDDCNTLN=1,
DLL_REEST=1, DDR_RESET=1, READY=0, PAUSE =0.
DLL_LOCK
I
LOCK output from DDRDLL
UPDATE
I
After ready goes high, you can use UPDATE to update code in DQSBUF, perform training (change
read_clk_sel) or write leveling (change dyndelay<>).
PAUSE
O
Connect to DQSBUF.PAUSE
STOP
O
Connect to ECLKSYNC.STOP
FREEZE
O
Connect to DDRDLL.FREEZE
UDDCNTLN
O
Connect to DDRDLL.UDDCNTLN
DLL_RESET
O
Reset to DDRDLL
DDR_RESET
O
Reset to all IDDRX, ODDRX, OSHX components, DQSBUF, and CLKDIV
READY
O
Indicate that startup is finished and RX circuit is ready to operate.
9.1.4. BW_ALIGN
This module is used to perform 7:1 video RX bit and word alignment. This module is optional and can be enabled in
Clarity Designer.
RX_SCLK
RXCLK_WORD <6:0>
UPDATE
PLL_LOCK
RST
PHASESTEP
PHASEDIR
ALIGNWORD
WINDOW_SIZE
BIT_LOCK
WORD_LOCK
READY
BW_ALIGN
Figure 9.4. BW_ALIGN Ports