ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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52 FPGA-TN-02035-1.3
Table 7.1 explains the various configurations options available for SDR modules.
Table 7.1. SDR Configuration Parameters
Type of Interface (Transmit or Receive)
I/O Standard for this Interface
I/O Standard to be used for the interface
Bus Width for this Interface
Bus size for the interface
Clock Frequency for this
Interface
This is the calculated from the clock
frequency entered.
Interface selected based on previous
entries
Transmit: GOREG_TX.SCLK
Receive: GIREG_RX.SCLK (default)
Option to invert the clock Input to the
I/O Register
Data input can be optionally delayed
using the DELAY block.
If Interface Type = Receive
then:
Bypass,
Static Default
Dynamic Default
Static User-Defined
Dynamic User-Defined
If Interface Type = Transmit
then:
Bypass,
Static User-Defined
Dynamic User-Defined
If Delay type selected above is user-
defined, delay values can be entered
with this parameter
*
Note: When Data Path Delay value is:
Bypass: No delay cell is used.
Static Default: Static delay element DELAYG is used with attribute DEL_MODE set to SCLK_ZEROHOLD.
Static User-Defined: Static delay element DELAYG is used with attribute DEL_MODE set to USER_DEFINED.
Dynamic Default: Dynamic delay element DELAYF is used with attribute DEL_MODE set to SCLK_ZEROHOLD.
Dynamic User-Defined: Dynamic delay element DELAYF is used with attribute DEL_MODE = USER_DEFINED.
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