Lattice Semiconductor ECP5 - Diamond Programmer Requirements; Board Programming Switches

ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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4 FPGA-TN-02035-1.3
6.3.4. Write Implementation (LPDDR2 and LPDDR3 Address, Command, and Clock) ........................................... 42
6.4. DDR Memory Interface Design Rules and Guidelines ....................................................................................... 44
6.5. DDR2/DDR3 Memory Interface Termination Guidelines .................................................................................. 45
6.5.1. Termination for DQ, DQS, and DM ............................................................................................................... 45
6.5.2. Termination for CK ....................................................................................................................................... 45
6.5.3. Termination for Address, Commands, and Controls .................................................................................... 46
6.5.4. Termination for DDR3/DDR3L DIMM ........................................................................................................... 46
6.6. DDR Memory Interface Pinout Guidelines ........................................................................................................ 46
6.7. Pin Placement Considerations for Improved Noise Immunity .......................................................................... 47
7. Using Clarity Designer to Build and Plan High Speed DDR Interfaces ......................................................................... 49
7.1. Configuring DDR Modules in Clarity Designer ................................................................................................... 50
7.2. Configuring SDR Modules .................................................................................................................................. 50
7.3. Configuring DDR Generic modules .................................................................................................................... 53
7.4. Configuring 7:1 LVDS Interface Modules........................................................................................................... 57
7.5. Configuring DDR Memory Interfaces ................................................................................................................ 58
7.6. Building DDR Interfaces in Clarity Designer ...................................................................................................... 62
7.7. Planning DDR Interfaces in Clarity Designer ...................................................................................................... 63
8. DDR Software Primitives and Attributes ..................................................................................................................... 64
8.1. Input/Output DELAY .......................................................................................................................................... 64
8.2. DELAYF ............................................................................................................................................................... 65
8.3. DELAYG .............................................................................................................................................................. 65
8.4. DELAY Attribute Description ............................................................................................................................. 66
8.5. DDRDLL (Master DLL) ........................................................................................................................................ 66
8.5.1. DDRDLLA ....................................................................................................................................................... 66
8.6. DLL Delay (DLLDEL) ............................................................................................................................................ 67
8.7. Generic DDR Input and Output Primitives ........................................................................................................ 68
8.8. Input DDR Primitives ......................................................................................................................................... 68
8.8.1. IDDRX1F ........................................................................................................................................................ 68
8.8.2. IDDRX2F ........................................................................................................................................................ 69
8.8.3. IDDR71B ........................................................................................................................................................ 69
8.9. Output DDR Primitives ...................................................................................................................................... 70
8.9.1. ODDRX1F ...................................................................................................................................................... 70
8.9.2. ODDRX2F ...................................................................................................................................................... 70
8.9.3. ODDR71B ...................................................................................................................................................... 71
8.10. Memory DDR Primitives .................................................................................................................................... 71
8.10.1. DQSBUF (DQS Strobe Control Block) ............................................................................................................ 71
8.10.2. DQSBUFM ..................................................................................................................................................... 72
8.11. Input and Output Memory DDR Primitives ....................................................................................................... 73
8.12. Memory Input DDR Primitives........................................................................................................................... 74
8.12.1. IDDRX2DQA .................................................................................................................................................. 74
8.13. Memory Output DDR Primitives for DQ Output ................................................................................................ 75
8.13.1. ODDRX2DQA ................................................................................................................................................. 75
8.14. Memory Output DDR Primitives for DQS Output .............................................................................................. 75
8.14.1. ODDRX2DQSB ............................................................................................................................................... 75
8.15. Memory Output DDR Primitives for Tristate Output Control ........................................................................... 76
8.15.1. TSHX2DQA .................................................................................................................................................... 76
8.15.2. TSHX2DQSA .................................................................................................................................................. 76
8.16. Memory Output DDR Primitives for Address and Command ............................................................................ 77
8.16.1. OSHX2A......................................................................................................................................................... 77
9. Soft IP Modules ........................................................................................................................................................... 78
9.1. Detailed Description of Each Soft IP .................................................................................................................. 78
9.1.1. GDDR_SYNC .................................................................................................................................................. 78
9.1.2. RX_SYNC ....................................................................................................................................................... 79
9.1.3. MEM_SYNC ................................................................................................................................................... 80