EasyManuals Logo

Lucent 5ESS DRM User Manual

Default Icon
642 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #600 background imageLoading...
Page #600 background image
BIT 1: DTIM - Indicates the associated AM CC sanity timer is
disabled.
BIT 0: MRF - Indicates that a processor recovery maintenance
reset function (MRF) has started. This bit is
simular to the MRF START bit except that it
is tied to the hardware signal (it does not need
to be read to be cleared).
Digit 20 = Current status of inhibits.
The bits are numbered from right to left as follows:
BIT 3 2 1 0
BIT 3: Indicates the AM’s automatic hardware checks have been
inhibited. The specific checks inhibited are: parity checking
(on the Address Translation Bus, Instruction Bus, Source Bus,
Micro-Controller, Cache), clock checking errors, My Store
Error A, Main Store timeout error, Data Manipulation Unit
error, and Store Address Controller error.
BIT 2: Indicates that reporting of non-fatal errors has been
inhibited for all units.
HARDWARE
CHECKS
INHIBITED
UNIX SYSTEM
ERROR
INTERRUPTS
INHIBITED
CACHE
BYPASSED
(NOT USED)
SIM
INHIBITED
HARDWARE STATUS BITS (5 of 6)
Figure A2-1 Hardware Status Bits (5 of 6)
APPENDIX 2
PROCESSOR RECOVERY MESSAGES
235-200-150
January 2003
Page A2-24 Issue 3.00

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Lucent 5ESS DRM and is the answer not in the manual?

Lucent 5ESS DRM Specifications

General IconGeneral
BrandLucent
Model5ESS DRM
CategoryControl Unit
LanguageEnglish