IN-4 Computer Group Literature Center Web Site
I
N
D
E
X
J23 test port header, pinouts 6-13
J24 debug port header, pinouts 6-13
J27 LCD & SPI connector, pinouts 6-22
J28 analog power connector, pinouts 6-12
jumper settings 6-3
jumpers
J1 backup power configuration 1-12, 
5-12
configuring 6-4
J3 boot ROM write protection, 
configuring 6-5
J4 boot ROM device selection
configuring 6-6
J5 test/debug port selection, 
configuring 6-7
J6 arbitration mode, configuring 6-8
J7 IDE interface configuration 6-9
J8, J9, J10 DRAM configuration 1-13
configuring 6-10
J11 DREQ# signal source, 
configuring 6-10
J4 boot ROM device selection 5-10
location 6-1
K
keep-alive power (KAPWR)
configuring backup 6-4
consumption 1-10
on-board source 5-11
keyboard interface 5-15
L
LAN circuits, fuse protection 5-20
LCD & SPI connector (J27), pinouts 6-22
LCD interface 5-16
LEDs 5-13
location 6-1
on-board, defined 6-29
legacy (IDE addressing) 6-9
lithium battery precautions 1-15
loading programs 4-3
low-battery indication 5-11
M
manual conventions xviii
manufacturers’ documents B-2
MBX models xv
memory
adding 1-12
boot ROM
configuring 5-10, 6-6
contents 3-2
DRAM 1-12, 5-9
EEPROM 4-1, 5-15
firmware requirements 3-2
Flash 3-2, 5-10, 6-6
NVRAM 5-11
write protecting boot ROM/Flash 6-5
mouse interface 5-15
MPC821 processor, description 5-8
MPC860 processor, description 5-7
MPC8xx bus interface 5-18
N
native (IDE addressing) 6-9
NVRAM 5-11
O
on-board battery 1-10, 5-11
life 5-11
replacing 1-14
on-board LEDs 6-29
P
P1 8xx/COMM connector, pinouts 6-17
P2 PCI connector, pinouts 6-23
P996.1 Standard 5-18
parallel connector (J13), pinouts 6-14
parallel interface 5-14
parallel port 5-17
PC/104
connector (J21/J22), pinouts 6-25
installation 1-7
stacking 1-8, 5-19