Nuvoton NuMicro MS51PC0AE - Page 339

MS51
Nov. 28, 2019 Page 339 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
PWMnCxL – PWMn Channel x Duty Low Byte, n = 0,1,2,3; x = 0,1,2,3,4,5
7
6
5
4
3
2
1
0
PWMnCx [7:0]
R/W
Bit
Name
Description
7:0
PWMnCx [7:0]
PWMnCx duty Low byte
This byte with PWMnCxH controls the duty of the output signal PGx from PWM generator.
Register
SFR Address
Description
Reset Value
PWM0C0L
DAH, Page 0
PWM0 Channel 0 Duty Low Byte
0000_0000 b
PWM0C1L
DBH, Page 0
PWM0 Channel 1 Duty Low Byte
0000_0000 b
PWM0C2L
DCH, Page 0
PWM0 Channel 2 Duty Low Byte
0000_0000 b
PWM0C3L
DDH, Page 0
PWM0 Channel 3 Duty Low Byte
0000_0000 b
PWM0C4L
CCH, Page 1
PWM0 Channel 4 Duty Low Byte
0000_0000 b
PWM0C5L
CDH, Page 1
PWM0 Channel 5 Duty Low Byte
0000_0000 b
PWM1_CH0L
B2H, Page 2
PWM1 Channel 0 Duty Low Byte
0000_0000 b
PWM1_CH1L
B3H, Page 2
PWM1 Channel 1 Duty Low Byte
0000_0000 b
PWM2_CH0L
C2H, Page 2
PWM2 Channel 0 Duty Low Byte
0000_0000 b
PWM2_CH1L
C3H, Page 2
PWM2 Channel 1 Duty Low Byte
0000_0000 b
PWM3_CH0L
D2H, Page 2
PWM3 Channel 0 Duty Low Byte
0000_0000 b
PWM3_CH1L
D3H, Page 2
PWM3 Channel 1 Duty Low Byte
0000_0000 b