Nuvoton NuMicro MS51PC0AE - Page 340

MS51
Nov. 28, 2019 Page 340 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
PWM0DTEN – PWM Dead-time Enable
Register
SFR Address
Reset Value
PWM0DTEN
F9H, Page 0, TA protected
0000_0000 b
7
6
5
4
3
2
1
0
-
-
-
PWM0DTCNT.
8
-
PDT45EN
PDT23EN
PDT01EN
-
-
-
R/W
-
R/W
R/W
R/W
Bit
Name
Description
4
PDTCNT8
PWM0 dead-time counter bit 8
See PWM0DTCNT register.
2
PDT45EN
PWM0C4/5 pair dead-time insertion enable
This bit is valid only when PWM0C4/5 is under complementary mode.
0 = No delay on P0G4/P0G5 pair signals.
1 = Insert dead-time delay on the rising edge of P0G4/P0G5 pair signals.
1
PDT23EN
PWM0_CH2/3 pair dead-time insertion enable
This bit is valid only when PWM0_CH2/3 is under complementary mode.
0 = No delay on P0G2/P0G3 pair signals.
1 = Insert dead-time delay on the rising edge of P0G2/P0G3 pair signals.
0
PDT01EN
PWM0C0/1 pair dead-time insertion enable
This bit is valid only when PWM0C0/1 is under complementary mode.
0 = No delay on P0G0/P0G1 pair signals.
1 = Insert dead-time delay on the rising edge of P0G0/P0G1 pair signals.