NXP Semiconductors MPC5777M - Page 147

Document revision history
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 147
2 4/2013
Electrical characteristics—Flash memory electrical characteristics
Section 3.15, Flash memory electrical characteristics
• This section completely revised.
Electrical characteristics—AC specifications—Debug and Calibration
Table 46 (JTAG pin AC electrical characteristics,):
• Specification change: t
JCYC
(TCK cycle time) now consists of a single
specification—minimum value is 100 ns. Footnotes from previous entries have been
removed.
• Specification change: t
TDOHZ
(TCK low to TDO high impedance) is now 15 ns (was 16)
• Classification change: All specifications are “D” (were “P” and “C”)
Table 47 (Nexus debug port timing)
• New specification: t
EVTIPW
(EVTI pulse width)
• New specification: t
EVTOPW
(EVTO pulse width)
• Clarification: footnote added to T
CYC
, defining it as the system clock period
• Specification change: TDO propagation delay from falling edge of TCK max is 16 ns
(was 12.5 ns)
• Specification change: TCK cycle time is min value is 2 t
CYC
(was 4)
• Specification change: Absolute minimum TCK cycle time min value is 40 ns (was 25)
• Specification change: TDI Data Hold Time min value is 5 ns (was 17.5)
• Specification change: TMS Data Hold Time min value is 5 ns (was 17.5)
• TDO propagation delay from falling edge of TCK max value is 16 ns (was 12.5)
• Specification change: t
TCYC
(absolute minimum TCK cycle time) now consists of two
specifications—one with TDO sampled on posedge of TCK and one sampled with TDO
sampled on negedge of TCK.
Table 48 (Aurora LVDS interface timing specifications)
• Specification change: Data rate typ. value is undefined (was 1200 Mbps)
• Specification change: Data rate max. value is 1250 Mbps (was “Typ+1%”)
Table 49 (Aurora debug port timing)
• Specification change: t
REFCLK
(Reference clock frequency) max value is 1250 MHz
(was 1200)
• Specification change: OUI (Aurora lane unit interval) is now specified by data rate
• Characteristic vs. Requirement change: J
D
(Transmit lane deterministic jitter) is “SR”
(was “CC”)
• Characteristic vs. Requirement change: J
T
(Transmit lane total jitter) is “SR” (was “CC”)
Electrical characteristics—AC specifications—DSPI
Section 3.19.2, DSPI timing with CMOS and LVDS pads: Substantive changes to entire
section, including reclassification of content as:
• Table 51 (DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0,
CPHA = 0 or 1)
• Table 52 (DSPI CMOS master modified timing (full duplex and output only) –
MTFE = 1, CPHA = 0 or 1)
• Table 54 (DSPI LVDS slave timing – full duplex – modified transfer format
(MTFE = 0/1))
• Table 55 (DSPI LVDS master timing – output only – timed serial bus mode TSB = 1 or
ITSB = 1, CPOL = 0 or 1, continuous SCK clock,)
• Table 56 (DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or
ITSB = 1, CPOL = 0 or 1, continuous SCK clock
,
)
Table 76. Revision history (continued)
Revision Date Description of changes