NXP Semiconductors QorIQ LX2160A - Page 11

Core Complex
Basic Peripherals and Interconnect
Accelerators and Memory Control
Networking Elements
SMMUs
2 MB Packet Express Buffer
DCE - 100G
QBMan
WRIOP
SEC - 50G
SATA3
SATA3
SATA3
SATA3
24 lanes at up to 25 GHz
x8 Gen4 PCIe
x8 Gen4 PCIe
x4 Gen4 PCIe
x4 Gen4 PCIe
x4 Gen4 PCIe
x4 Gen4 PCIe
Cache Coherent Interconnect
4 x UART
8 x I2C
2 x SDHC/eMMC
3 x SPI Flash
FlexSPI
2 x USB 3.0
+ PHY
4 x GPIO
2 x WDOG
System control
Internal
BootROM
Security fuses
Security Monitor
Power
Management
Service Processor
System interfaces
2 x CAN-FD
2 x Flextimers
72-bit
(64-bit
+ ECC)
DDR4
memory
controller
72-bit
(64-bit
+ ECC)
DDR4
memory
controller
130 Gbps
1 / 2.5 / 10 / 25 / 40 / 50 / 100
Ethernet
qDMA
1 MB Chonerent
L2 Cache
Arm®
A72 core
ARM®
A72 Core
1 MB Coherent
L2 C
ache
1 MB Chonerent
L2 Cache
Arm®
A72 core
Arm®
A72 core
1 MB Coherent
L2 C
ache
1 MB Chonerent
L2 Cache
Arm®
A72 core
Arm®
A72 core
1 MB Coherent
L2 C
ache
1 MB Chonerent
L2 Cache
Arm®
A72 core
Arm®
A72 core
1 MB Coherent
L2 C
ache
1 MB Chonerent
L2 Cache
Arm®
A72 core
Arm®
A72 core
1 MB Coherent
L2 C
ache
1 MB Chonerent
L2 Cache
Arm®
A72 core
Arm®
A72 core
1 MB Coherent
L2 C
ache
1 MB Chonerent
L2 Cache
Arm®
A72 core
Arm®
A72 core
1 MB Coherent
L2 C
ache
1 MB Chonerent
L2 Cache
Arm®
A72 core
Arm®
A72 core
1 MB Coherent
L2 C
ache
8 MB Platform Cache
1 MB Chonerent
L2 Cache
Arm®
A72 core
1 MB Coherent
L2 C
ache
Figure 1-1. LX2160A block diagram
The figure below shows the LX2160ARDB block diagram.
Chapter 1 LX2160ARDB Overview
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
NXP Semiconductors 11