NXP Semiconductors QorIQ LX2160A - Page 5

Section number Title Page
3.28 Power Status 1 (PWR_STAT1)...................................................................................................................................... 92
3.29 Power Status 2 (PWR_STAT2)...................................................................................................................................... 94
3.30 Clock Control Registers..................................................................................................................................................95
3.31 Clock Speed 1 (CLK_SPD1).......................................................................................................................................... 95
3.32 Clock ID/Status (CLK_ID).............................................................................................................................................96
3.33 Reset Control Registers...................................................................................................................................................97
3.34 Reset Control (RST_CTL)..............................................................................................................................................98
3.35 Reset Status (RST_STAT)..............................................................................................................................................99
3.36 Reset Event Trace (RST_REASON).............................................................................................................................. 100
3.37 Reset Force 1 (RST_FORCE1).......................................................................................................................................101
3.38 Reset Force 2 (RST_FORCE2).......................................................................................................................................102
3.39 Reset Force 3 (RST_FORCE3).......................................................................................................................................103
3.40 Reset Mask 1 (RST_MASK1)........................................................................................................................................ 104
3.41 Reset Mask 2 (RST_MASK2)........................................................................................................................................ 106
3.42 Reset Mask 2 (RST_MASK3)........................................................................................................................................ 107
3.43 Board Configuration Registers....................................................................................................................................... 108
3.44 Board Configuration 0 (BRDCFG0)...............................................................................................................................108
3.45 Board Configuration 1 (BRDCFG1)...............................................................................................................................109
3.46 Board Configuration 2 (BRDCFG2)...............................................................................................................................110
3.47 Board Configuration 3 (BRDCFG3)...............................................................................................................................111
3.48 Board Configuration 4 (BRDCFG4)...............................................................................................................................112
3.49 DUT Configuration Registers.........................................................................................................................................114
3.50 DUT Configuration 0 (DUTCFG0)................................................................................................................................ 114
3.51 DUT Configuration 1 (DUTCFG1)................................................................................................................................ 115
3.52 DUT Configuration 2 (DUTCFG2)................................................................................................................................ 116
3.53 DUT Configuration 6 (DUTCFG6)................................................................................................................................ 117
3.54 DUT Configuration 11 (DUTCFG11)............................................................................................................................ 118
3.55 DUT Configuration 12 (DUTCFG12)............................................................................................................................ 119
3.56 IRQ Management Registers............................................................................................................................................120
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
NXP Semiconductors 5