11 High-speed Counters
11-6
CP2E CPU Unit Software User’s Manual(W614)
z Wiring Example for High-speed Counter Input Terminals
Using a 24-VDC Open-collector Encoder
The following example shows the connections of an encoder with phase-A, phase-B, and phase-Z
inputs to high-speed counter 0.
Writing the Ladder Program
Execution Program Reference
Generating interrupts for the
high-speed counter PV (num-
ber of pulses) and perform
high-speed processing.
Specify interrupt tasks with CTBL
instructions.
11-3 High-speed
Counter Interrupts
Reading the high-speed
counter PV (number of
pulses).
Read the high-speed counter PV from
the Auxiliary Area and convert it to
position or length data using instruc-
tions or measure the length using con-
mparison instructions such as =, >,
and <.
11-2-4 Reading the
Present Value
Reading the high-speed
counter frequency (speed).
Execute a PRV instruction. 11-2-5 Frequency
Measurement
0V
+24V
0.00
0.01
0.04
COM
(COM 24V
)
0.00
0.01
0.04
COM
0V
24V
0V
IA
IB
IZ
Encoder
(power supply: 24 VDC)
Example: E6B2-CWZ6C
NPN open-collector output
Black
Phase A
White
Phase B
Orange
Phase Z
Brown+Vcc
Blue 0V(COM)
24 VDC power supply
CP2E CPU Unit
(Differential Phase Input Mode)
(High-speed counter 0: Phase A 0 V)
(High-speed counter 0: Phase B 0 V)
(High-speed counter 0: Phase Z 0 V)
Power provided
Encoder
(Do not use the same I/O power supply as other equipment.)
Power supply
Shielded twisted-pair cable
CP2E CPU Unit
Phase A
Phase B
Phase Z
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