6-105
6
PID Control Block
The following diagram shows the PID control block in the Inverter.
Fig 6.81 PID Control Block Diagram
Option Card
Serial Com
Analog Input A1/
A2*
Pulse Train Inp.
D1-16
D1-02
Output
frequency
P
1/t
1/t
Z
-1
b1-01
1
2
3
Frequency Reference
using multi-step
command
Frequency reference
(U1-01)
PID Set Point
(U1-38)
Proportional
gain
b5-02
I-time
b5-03
I - limit
b5-04
PID Limit
b5-06
PID delay time
b5-08
+
+
+
+
b5-01=0
ON
PID control is OFF under the
following conditions:
- b5-01=0
- During JOG command is input
- H3-=19 and the terminal
status is ON
Upper limit
Fmax x109%
+
+
b5-01=3 or 4
b5-01=1 or 2
Upper limit
Fmax x109%
Lower limit
Fmax x109%
Lower limit 0
0
MEMOBUS Reg. 06H
PID target value
Integral Hold
H1-=31
Integral Reset
H1-=30
PID Output
Caracteristic
b5-09
b5-11
1
0
Enable / Disable reverse operation
when PID output is negativ
Constant b5-19
b5-18=1
0
PID SFS
b5-17
PID SFS cancel
H1-=34
0
1
Frequency Reference / PID Target
PID Target
o1-03
Scaling
1
Reg. 0Fh, bit 1
PID Feedback
Terminal A2/A1*
H3-09=B
1
0
Z
-1
1
0
1
0
PID Input
Characteristic
H1-=35
1
0
Z
-1
PID SFS
b5-17
PID SFS cancel
H1-=34
0
1
PID Input
(U1-36)
+
-
1
0
b5-28
PID Feedback
(U1-24)
b5-07
+
+
-
+
b5-10
PID Output
Gain
PID offset
+
-
b5-15
Sleep Level
RUN
on/off
b5-16
Delay
Timer
Sleep Function
SFS
OFF
P
b5-29
4
D1-01
Puls Train Input
PID target value
Analog Input A2/A1*
H6-01=2
H3-09=C
Pulse Train Inp.
PID Monitor
Feedback Sel.
U1-
B5-31 0
H6-01=1
Z
-1
b5-05
+
+
1 or 3
2 or 4
b5-01
Differential
Time
* If analog input A2 is set as master reference input (H3-13=1),
analog input A1 can be selected for PID target or PID
feedback using parameter H3-09
H3-09 B
H6-01 1
B5-31=0
H3-09 C
b5-18 = 1
H6-01 2
Z
-1
b5-05
b5-01
2 or 4
1 or 3
+
+
+
+
Square Root
Feedback
PID output monitor
(U1-37)
b5-28
10
Square Root
Feedback
Monitor
-200%
200%
3 or 4 1 or 2
b5-01