Once the
instrument
has
requested
service, the service
request
enable
register must
be set up
again before
another
request
can be made. The
command
*SREn,
with which
this
is done also resets the
RQS
bit (bit
64)
in the status register.
The service request
enable register
can be read with the command *SRE?
2.5.3 Assigning
Error
Events
The error
bit
in the
status byte
register
may have assigned to it any combination of
the events stored
in the event status
register
(ESR). This register (read only) can
be
read
with
the command
*ESR?
Error events
are assigned by
setting
the appropriate bit(s) in the event
status
enable
register (ESE) with
the command
*ESErc.
See the example in Fig 7.4.
The event
status register is cleared by the commands break (BK),
event status
enable
(*ESE/i),
event status query (*ESR?),
clear
status (*CLS), reset
(*RST), initialize (TTl)
and reset
(TT2), and on power-up.
The
command *ESEn
also resets the ESB bit
(bit
32)
in the
status byte register.
Remember that
if an interrupt is required for the error event(s)
then the error bit in
the
service request enable
mask must be set to
*1*
(*SRE32).
EVENT STATUS
ENABLE
(
set-up code
=
*ESE 1
7)
0
0 0
1
0
0 0
1
m
.
'
POW«t'.
:
ON
• :«4
:
USER
REQUEST
32
COM
?'Q
ERROR
16
EXEC.
ERROR
6
DEV DEP
ERROR
4
"
QUERY
ERROR
2
REQUEST
CONTROL
1
OPERA'T.
COMPL.
EVENTSTATUS
REGISTER
^
Whichever of these
bits is set first
sets
the error bit in
the status
byte
register.
Fig
7.4 Assigning
fr
execution error
n
and
*
operation
complete
” to
the
status byte
error
bit.
The
significance
of the event bits is as follows:
Bit
128
Power
On
64 User
Request
32
Command Error
16
Execution Error
8 Device
Dependent
Error
Event
Set
when the power
supply
has
been switched
off and on.
Not
used.
Set by
Error
01 and Error 02.
Set by
Error
03 and Error
61.
Set by
any other errors or
warnings.
4
Query Error Set if
an attempt is made
to read non-existent
data, or if a
reading
is aborted
before all
data is read.
2
Request
Control Not
used.
1
Operation
Complete
Set
when
the instrument
has
completed an operation.
This
bit must first
be enabled
by an
operation
complete
(*OPC) command.
JWS/1
260/2
7.9
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