4.13 I2C interface
The STWBC86 can operate fully independent, that is, without being interfaced with a host system. In applications
in which the STWBC86 is a part of peripherals managed by the host system, the two SDA and SCL pins could be
connected to the existing I2C bus. The device works as an I2C slave and supports standard (100 kbps), fast (400
kbps), and fast mode plus (1 Mbps) data transfer modes. The STWBC86 has been assigned a 0x61 7-bit
hardware address.
The pins are up to 3.3 V tolerant, and the pull-up resistors should be selected as a trade-off between
communication speed (lower resistors lead to faster edges) and data integrity (the input logic levels must be
guaranteed to preserve communication reliability). When the bus is idle, both SDA and SCL lines are pulled
HIGH.
4.13.1 Data validity
The data on the SDA line remains stable during the high state of every SCL clock pulse. The high and low states
of the SDA line only change when the SCL clock signal is low.
4.13.2 Start and stop conditions
Both the SDA and the SCL lines remain high when the I2C bus is not busy. A START condition is indicated by a
high-to-low transition of the SDA line when SCL is HIGH, while the STOP condition is indicated by a low-to-high
transition of the SDA line when SCL is HIGH. A STOP condition must be sent before each START condition.
4.13.3 Byte format
Every byte transferred over the SDA line contains 8 bits. Each byte received by STWBC86 is generally followed
by an acknowledge (ACK) bit. The most significant bit (MSB) is transferred first. A single data bit is transferred
during each clock pulse.
The device generates an ACK pulse (by pulling the SDA line low during the acknowledge clock pulse) to confirm a
correct device address or data bytes reception.
4.13.4 Interface protocol
The interface protocol is composed of:
• A start condition (START)
• A device address + R/W bit (read =1 / write =0)
• A register H address byte
• A register L address byte
• A sequence of n data bytes (each data byte must be acknowledged by the receiver)
• A stop condition (STOP)
The register address byte determines the first register in which the read or write operation takes place. When a
read or write operation is finished, the register address is automatically incremented.
Frequently used acronyms:
SAD: Slave Address; SUB AD: Subaddress; SR: Repeated start; R: Read; W: Write; SAK: Slave Acknowledge;
MAK: Master Acknowledge; NMAK: No Master Acknowledge.
4.13.5 Writing to a single register
Writing to a single register begins with a START condition followed by the device address 0xC2 (7-bit device
address plus R/W bit cleared), two bytes of the register pointer and the data byte to be written in the destination
register. Each transmitted byte is acknowledged by the STWBC86 through an ACK pulse.
UM3161
I2C interface
UM3161 - Rev 1
page 39/78
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