4.13.8 Reading from multiple registers with incremental addressing
Similarly, to multiple bytes (page) writing, reading from subsequent registers relies on an auto-increment of the
register: The master can extend data reading to the following registers by generating an ACK pulse at the end of
each byte. Data reading starts immediately, and the stream is terminated by an NMAK at the end of the last data
byte, followed by a STOP condition.
Figure 54. Reading from multiple registers
4.14 GPIOx and INTB pins
GPIO0 through GPIO7 are programmable general-purpose I/O pins. These pins can be configured as inputs or
outputs (push-pull or open-drain) and assigned various functions.
Table 3. GPIO functions
Code
I/O Function
0x01 I Pull-up
0x02 I Pull-down
0x03 O Open drain (Active high)
0x04 O Open drain (Active low)
0x05 O Interrupt (Open drain)
0x06 O Firmware ready
0x1A O Power transfer on – high when in power transfer, low in standby and ping state
0x1E O
Tx error – high in error state which causes Tx to stop pinging. Conditions which cause this error can be set in the
GUI
The INTB (GPIO6) pin is an interrupt output line that can be assigned to any internal interrupt condition and used
to inform the host system about a specific event.
4.15
Interrupt registers
There are 4 bits (enable, clear, latch, and status) assigned to each interrupt sorted into separate tabs.
The Enable tab can be used to either enable the corresponding interrupt (write), or to check whether the interrupt
is already enabled (read).
The Latch tab can be used to determine which interrupts have been triggered (read only). After being triggered,
the bit remains set to 1 until cleared by writing a 1 into the corresponding clear register (write only).
The Status tab can be used to determine which interrupt is being triggered at the moment (read only). The status
bit goes back to zero after the triggering condition is removed.
UM3161
GPIOx and INTB pins
UM3161 - Rev 1
page 41/78
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