DocID13902 Rev 15 1114/1128
RM0008 Revision history
1120
12-Jan-2011 12
Added Section 1: Overview of the manual
Added FSMC boundary addresses to Table 3 on page 51
Added paragraph on HSI to Programming and erasing the Flash memory on page 60
Updated Table 11.12.12: ADC injected sequence register (ADC_JSQR) on page 249
Added “VREF shared with ADC in Section 12.1: DAC introduction on page 253
Updated example in Section 14.4.19: TIM1&TIM8 DMA control register (TIMx_DCR) on
page 356 and other timer sections.
Updated description of counter operation in Section 15.3.12: Encoder interface mode
Moved caution paragraph from RTC_PRLH to RTC PRLL in Section 18.4: RTC registers
Updated Table 108: NOR Flash/PSRAM controller: example of supported memories
and transactions on page 507Changed data phase to data setup phase in FSMC WAIT
management in asynchronous accesses on page 523
Added note on shared SRAM for USB and CAN to Section 23.2: USB main features on
page 613
Updated LEC description in CAN error status register (CAN_ESR) on page 673
Updated CRCNEXT description in Section 25.3.6: CRC calculation on page 706
Corrected Figure 264: PCM standard waveforms (16-bit) on page 722
Updated Table 184: Audio-frequency precision using standard 25 MHz and PLL3
(connectivity line devices only) and Table 185: Audio-frequency precision using standard
14.7456 MHz and PLL3 (connectivity line devices only) on page 726
Updated BERR description in Section 26.6.6: I2C Status register 1 (I2C_SR1) on
page 770
Updated note 1 in Section 26.6.8: I2C Clock control register (I2C_CCR) on page 775
Table 235. Document revision history (continued)
Date Revision Changes
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