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1127/1128 DocID13902 Rev 15

WWDG_CR . . . . . . . . . . . . . . . . . . . . . . . . . .495

WWDG_SR

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Main Page

Default Chapter2
- Table of Contents2
Overview of the Manual40
- Table 1. Sections Related to each Stm32F10Xxx Product40
- Table 2. Sections Related to each Peripheral43
Documentation Conventions47
- List of Abbreviations for Registers47
- Glossary47
- Peripheral Availability47
Memory and Bus Architecture48
- System Architecture48
- Figure 1. System Architecture (Low-, Medium-, XL-Density Devices)48
- Figure 2. System Architecture in Connectivity Line Devices49
- Memory Organization50
- Memory Map51
- Boot Configuration61
- Table 9. Boot Modes61
CRC Calculation Unit64
- CRC Introduction64
- CRC Main Features64
- Figure 3. CRC Calculation Unit Block Diagram64
- CRC Functional Description65
- CRC Registers65
Power Control (PWR)67
- Power Supplies67
- Power Supply Supervisor70
- Low-Power Modes72
- Power Control Registers77
Backup Registers (BKP)81
- BKP Introduction81
- BKP Main Features81
- BKP Functional Description82
  - Tamper Detection82
  - RTC Calibration82
- BKP Registers83
Low-, Medium-, High- and XL-Density Reset and Clock Control (RCC)90
- Reset90
- Clocks92
Connectivity Line Devices: Reset and Clock Control (RCC)123
- Reset123
- Clocks125
- RCC Registers132
General-Purpose and Alternate-Function I/Os (Gpios and Afios)159
- GPIO Functional Description159
- GPIO Registers171
- Alternate Function I/O and Debug Configuration (AFIO)175
- AFIO Registers183
- GPIO and AFIO Register Maps194
- Table 59. GPIO Register Map and Reset Values194
- Table 60. AFIO Register Map and Reset Values194
Interrupts and Events196
- Nested Vectored Interrupt Controller (NVIC)196
- External Interrupt/Event Controller (EXTI)205
- EXTI Registers210
Analog-To-Digital Converter (ADC)214
- ADC Introduction214
- ADC Main Features215
- ADC Functional Description215
  - Figure 22. Single ADC Block Diagram216
  - Table 65. ADC Pins217
  - ADC Clock218
  - ADC On-Off Control218
  - Channel Selection218
  - Single Conversion Mode218
  - Continuous Conversion Mode219
  - Figure 23. Timing Diagram219
  - Timing Diagram219
  - Analog Watchdog220
  - Figure 24. Analog Watchdog Guarded Area220
  - Scan Mode220
  - Table 66. Analog Watchdog Channel Selection220
  - Figure 25. Injected Conversion Latency221
  - Injected Channel Management221
  - Discontinuous Mode222
- Calibration222
- Data Alignment223
- Figure 26. Calibration Timing Diagram223
- Figure 27. Right Alignment of Data223
- Figure 28. Left Alignment of Data223
- Channel-By-Channel Programmable Sample Time224
- Conversion on External Trigger224
- Table 67. External Trigger for Regular Channels for ADC1 and ADC2224
- Table 68. External Trigger for Injected Channels for ADC1 and ADC2225
- Table 69. External Trigger for Regular Channels for ADC3225
- Table 70. External Trigger for Injected Channels for ADC3225
- DMA Request226
- Dual ADC Mode227
  - Figure 29. Dual ADC Block Diagram228
  - Figure 30. Injected Simultaneous Mode on 4 Channels229
  - Injected Simultaneous Mode229
  - Regular Simultaneous Mode229
  - Fast Interleaved Mode230
  - Figure 31. Regular Simultaneous Mode on 16 Channels230
  - Figure 32. Fast Interleaved Mode on 1 Channel in Continuous Conversion Mode230
  - Slow Interleaved Mode230
  - Alternate Trigger Mode231
  - Figure 33. Slow Interleaved Mode on 1 Channel231
  - Figure 34. Alternate Trigger: Injected Channel Group of each ADC231
  - Combined Regular Simultaneous + Alternate Trigger Mode232
  - Combined Regular/Injected Simultaneous Mode232
  - Figure 35. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Model232
  - Independent Mode232
  - Combined Injected Simultaneous + Interleaved233
  - Figure 36. Alternate + Regular Simultaneous233
  - Figure 37. Case of Trigger Occurring During Injected Conversion233
  - Figure 38. Interleaved Single Channel with Injected Sequence CH11, CH12233
- Temperature Sensor234
- Figure 39. Temperature Sensor and VREFINT Channel Block Diagram234
- ADC Interrupts235
- Table 71. ADC Interrupts235
- ADC Registers236
  - ADC Status Register (ADC_SR)236
  - ADC Control Register 1 (ADC_CR1)237
  - ADC Control Register 2 (ADC_CR2)239
  - ADC Sample Time Register 1 (ADC_SMPR1)243
  - ADC Sample Time Register 2 (ADC_SMPR2)244
  - ADC Injected Channel Data Offset Register X (Adc_Jofrx)(X=1244
  - ADC Watchdog High Threshold Register (ADC_HTR)245
  - ADC Watchdog Low Threshold Register (ADC_LTR)245
  - ADC Regular Sequence Register 1 (ADC_SQR1)246
  - ADC Regular Sequence Register 2 (ADC_SQR2)247
  - ADC Regular Sequence Register 3 (ADC_SQR3)248
  - ADC Injected Sequence Register (ADC_JSQR)249
  - ADC Injected Data Register X (Adc_Jdrx) (X= 1250
  - ADC Regular Data Register (ADC_DR)250
  - 11.12.15 ADC Register Map251
  - Table 72. ADC Register Map and Reset Values251
Digital-To-Analog Converter (DAC)253
- DAC Introduction253
- DAC Main Features253
- Table 73. DAC Pins254
- Figure 40. DAC Channel Block Diagram254
- DAC Functional Description255
- Dual DAC Channel Conversion260
- DAC Registers264
Direct Memory Access Controller (DMA)273
- DMA Introduction273
- DMA Main Features273
- Figure 48. DMA Block Diagram in Connectivity Line Devices274
- DMA Functional Description275
- DMA Registers284
Advanced-Control Timers (TIM1&TIM8)292
- TIM1&TIM8 Introduction292
- TIM1&TIM8 Main Features293
- Figure 52. Advanced-Control Timer Block Diagram294
- TIM1&TIM8 Functional Description295
- TIM1&TIM8 Registers333
- Break Feature350
General-Purpose Timers (TIM2 to TIM5)360
- TIM2 to TIM5 Introduction360
- Timx Main Features361
- Timx Functional Description362
- Timx2 to TIM5 Registers397
General-Purpose Timers (TIM9 to TIM14)418
- TIM9 to TIM14 Introduction418
- TIM9 to TIM14 Main Features419
  - TIM9/TIM12 Main Features419
  - Figure 146. General-Purpose Timer Block Diagram (TIM9 and TIM12)419
  - TIM10/TIM11 and TIM13/TIM14 Main Features420
  - Figure 147. General-Purpose Timer Block Diagram (TIM10/11/13/14)420
- TIM9 to TIM14 Functional Description421
  - Time-Base Unit421
  - Counter Modes422
  - Figure 148. Counter Timing Diagram with Prescaler Division Change from 1 to 2422
  - Figure 149. Counter Timing Diagram with Prescaler Division Change from 1 to 4422
  - Figure 150. Counter Timing Diagram, Internal Clock Divided by 1423
  - Figure 151. Counter Timing Diagram, Internal Clock Divided by 2423
  - Figure 152. Counter Timing Diagram, Internal Clock Divided by 4424
  - Figure 153. Counter Timing Diagram, Internal Clock Divided by N424
  - Clock Selection425
  - Figure 156. Control Circuit in Normal Mode, Internal Clock Divided by 1426
  - Figure 157. TI2 External Clock Connection Example426
  - Capture/Compare Channels427
  - Figure 158. Control Circuit in External Clock Mode 1427
  - Figure 159. Capture/Compare Channel (Example: Channel 1 Input Stage)427
- Input Capture Mode428
- Figure 160. Capture/Compare Channel 1 Main Circuit428
- Figure 161. Output Stage of Capture/Compare Channel (Channel 1)428
- PWM Input Mode (Only for TIM9/12)429
- Forced Output Mode430
- Figure 162. PWM Input Mode Timing430
- Output Compare Mode431
- PWM Mode432
- Figure 163. Output Compare Mode, Toggle on OC1432
- One-Pulse Mode433
- Figure 164. Edge-Aligned PWM Waveforms (ARR=8)433
- Figure 165. Example of One Pulse Mode433
- TIM9/12 External Trigger Synchronization434
- Figure 166. Control Circuit in Reset Mode435
- Figure 167. Control Circuit in Gated Mode436
- Figure 168. Control Circuit in Trigger Mode436
- Timer Synchronization (TIM9/12)437
- Debug Mode437
- TIM9 and TIM12 Registers437
  - TIM9/12 Control Register 1 (Timx_Cr1)437
  - 9/12TIM9/12 Slave Mode Control Register (Timx_Smcr)439
  - Table 89. Timx Internal Trigger Connection439
  - TIM9/12 Interrupt Enable Register (Timx_Dier)440
  - TIM9/12 Status Register (Timx_Sr)441
  - TIM9/12 Event Generation Register (Timx_Egr)442
  - TIM9/12 Capture/Compare Mode Register 1 (Timx_Ccmr1)444
  - TIM9/12 Capture/Compare Enable Register (Timx_Ccer)447
  - TIM9/12 Counter (Timx_Cnt)448
  - TIM9/12 Prescaler (Timx_Psc)448
  - TIM9/12 Auto-Reload Register (Timx_Arr)448
  - Table 90. Output Control Bit for Standard Ocx Channels448
  - TIM9/12 Capture/Compare Register 1 (Timx_Ccr1)449
  - TIM9/12 Capture/Compare Register 2 (Timx_Ccr2)449
  - TIM9/12 Register Map449
  - Table 91. TIM9/12 Register Map and Reset Values450
- TIM10/11/13/14 Registers452
  - TIM10/11/13/14 Control Register 1 (Timx_Cr1)452
  - TIM10/11/13/14 Status Register (Timx_Sr)453
  - TIM10/11/13/14 Event Generation Register (Timx_Egr)453
  - TIM10/11/13/14 Capture/Compare Mode Register 1454
    - (Timx_Ccmr1)454
  - TIM10/11/13/14 Capture/Compare Enable Register457
    - (Timx_Ccer)457
    - Table 92. Output Control Bit for Standard Ocx Channels457
  - TIM10/11/13/14 Counter (Timx_Cnt)458
  - TIM10/11/13/14 Prescaler (Timx_Psc)458
  - TIM10/11/13/14 Auto-Reload Register (Timx_Arr)458
  - TIM10/11/13/14 Capture/Compare Register 1 (Timx_Ccr1)459
  - TIM10/11/13/14 Register Map459
  - Table 93. TIM10/11/13/14 Register Map and Reset Values459
Basic Timers (TIM6&TIM7)461
- TIM6&TIM7 Introduction461
- TIM6&TIM7 Main Features461
- TIM6&TIM7 Functional Description462
- TIM6&TIM7 Registers467
Real-Time Clock (RTC)473
- RTC Introduction473
- RTC Main Features474
- RTC Functional Description475
- RTC Registers478
Independent Watchdog (IWDG)485
- IWDG Introduction485
- IWDG Main Features485
- IWDG Functional Description485
- IWDG Registers487
Window Watchdog (WWDG)491
- WWDG Introduction491
- WWDG Main Features491
- WWDG Functional Description491
- Figure 183. Watchdog Block Diagram492
- How to Program the Watchdog Timeout493
- Figure 184. Window Watchdog Timing Diagram493
- Debug Mode494
- Table 98. Min-Max Timeout Value @36 Mhz (F PCLK1 )494
- WWDG Registers495
Flexible Static Memory Controller (FSMC)498
- FSMC Main Features498
- Block Diagram499
- AHB Interface500
  - Figure 185. FSMC Block Diagram500
  - Supported Memories and Transactions501
- External Device Address Mapping502
- NOR Flash/Psram Controller504
Secure Digital Input/Output Interface (SDIO)556
- SDIO Main Features556
- SDIO Bus Topology557
- Figure 206. SDIO "No Response" and "No Data" Operations557
- Figure 207. SDIO (Multiple) Block Read Operation557
- Figure 208. SDIO (Multiple) Block Write Operation558
- Figure 209. SDIO Sequential Read Operation558
- Figure 210. SDIO Sequential Write Operation558
- SDIO Functional Description559
  - Figure 211. SDIO Block Diagram559
  - Figure 212. SDIO Adapter560
  - SDIO Adapter560
  - Table 137. SDIO I/O Definitions560
  - Figure 213. Control Unit561
  - Figure 214. SDIO Adapter Command Path562
  - Figure 215. Command Path State Machine (CPSM)563
  - Figure 216. SDIO Command Transfer564
  - Table 138. Command Format564
  - Table 139. Short Response Format565
  - Table 140. Long Response Format565
  - Table 141. Command Path Status Flags565
  - Figure 217. Data Path566
  - Figure 218. Data Path State Machine (DPSM)567
  - Table 142. Data Token Format568
  - Table 143. Transmit FIFO Status Flags569
  - SDIO AHB Interface570
  - Table 144. Receive FIFO Status Flags570
- Card Functional Description571
  - Card Identification Mode571
  - Card Reset571
  - Operating Voltage Range Validation572
  - Card Identification Process572
  - Block Write573
  - Block Read574
  - Stream Access, Stream Write and Stream Read (Multimediacard Only)574
  - Erase: Group Erase and Sector Erase576
  - Wide Bus Selection or Deselection577
  - Protection Management577
  - Card Status Register580
  - Table 145. Card Status581
  - SD Status Register583
  - Table 146. SD Status583
  - Table 147. Speed Class Code Field585
  - Table 148. Performance Move Field585
  - Table 149. AU_SIZE Field586
  - Table 150. Maximum AU Size586
  - Table 151. Erase Size Field586
  - Table 152. Erase Timeout Field586
- SD I/O Mode587
- Table 153. Erase Offset Field587
- Commands and Responses588
- Table 154. Block-Oriented Write Commands589
- Table 155. Block-Oriented Write Protection Commands590
- Table 156. Erase Commands590
- Table 157. I/O Mode Commands590
- Response Formats591
  - Table 158. Lock Card591
  - Table 159. Application-Specific Commands591
  - R1 (Normal Response Command)592
  - R1B592
  - R2 (CID, CSD Register)592
  - R3 (OCR Register)592
  - Table 160. R1 Response592
  - Table 161. R2 Response592
  - R4 (Fast I/O)593
  - R4B593
  - Table 162. R3 Response593
  - Table 163. R4 Response593
  - Table 164. R4B Response593
  - R5 (Interrupt Request)594
  - Table 165. R5 Response594
  - Table 166. R6 Response594
- SDIO I/O Card-Specific Operations595
  - SDIO I/O Read Wait Operation by SDIO_D2 Signalling595
  - SDIO Read Wait Operation by Stopping SDIO_CK595
  - SDIO Suspend/Resume Operation596
  - SDIO Interrupts596
- CE-ATA Specific Operations596
  - Command Completion Signal Disable596
  - Command Completion Signal Enable596
  - CE-ATA Interrupt597
  - Aborting CMD61597
- HW Flow Control597
- SDIO Registers597
  - SDIO Power Control Register (SDIO_POWER)598
  - SDI Clock Control Register (SDIO_CLKCR)598
  - SDIO Argument Register (SDIO_ARG)599
  - SDIO Command Register (SDIO_CMD)600
  - SDIO Command Response Register (SDIO_RESPCMD)601
  - SDIO Response 1601
  - Table 167. Response Type and Sdio_Respx Registers601
  - SDIO Data Timer Register (SDIO_DTIMER)602
  - SDIO Data Length Register (SDIO_DLEN)602
  - SDIO Data Control Register (SDIO_DCTRL)603
  - SDIO Data Counter Register (SDIO_DCOUNT)604
  - SDIO Status Register (SDIO_STA)605
  - SDIO Interrupt Clear Register (SDIO_ICR)606
  - SDIO Mask Register (SDIO_MASK)608
  - SDIO FIFO Counter Register (SDIO_FIFOCNT)610
  - SDIO Data FIFO Register (SDIO_FIFO)611
  - SDIO Register Map611
  - Table 168. SDIO Register Map611
Universal Serial Bus Full-Speed Device Interface (USB)613
- USB Introduction613
- USB Main Features613
- USB Functional Description613
  - Figure 219. USB Peripheral Block Diagram614
  - Description of USB Blocks615
- Programming Considerations616
- USB Registers628
Controller Area Network (Bxcan)645
- Bxcan Introduction645
- Bxcan Main Features645
- Bxcan General Description646
- Bxcan Operating Modes648
- Test Mode650
Serial Peripheral Interface (SPI)690
- SPI Introduction690
- SPI and I 2 S Main Features691
  - SPI Features691
  - I 2 S Features692
- SPI Functional Description693
- Case of Continuous Transfers703
- Figure 243. TXE/BSY in Slave Transmit-Only Mode (BIDIMODE=0 and RXONLY=0) in the Case of704
- Figure 244. RXNE Behavior in Receive-Only Mode (BIDIRMODE=0 and RXONLY=1) in the Case of705
- Continuous Transfers705
- I 2 S Functional Description714
- SPI and I 2 S Registers733
Inter-Integrated Circuit (I 2 C) Interface743
- I 2 C Introduction743
- I 2 C Main Features744
- C Functional Description745
- I 2 C Interrupts763
- Table 189. I2C Interrupt Requests763
- Figure 277. I2C Interrupt Mapping Diagram764
- I 2 C Debug Mode765
- I 2 C Registers765
Universal Synchronous Asynchronous Receiver Transmitter (USART)778
- USART Introduction778
- USART Main Features779
- USART Functional Description780
- USART Interrupts809
- Table 198. USART Interrupt Requests809
- Figure 300. CTS Flow Control809
- USART Mode Configuration810
- USART Registers810
USB On-The-Go Full-Speed (OTG_FS)821
- OTG_FS Introduction821
- OTG_FS Main Features822
- OTG_FS Functional Description824
- OTG Dual Role Device (DRD)825
- USB Peripheral827
- USB Host831
- SOF Trigger836
- Power Options837
- Dynamic Update of the OTG_FS_HFIR Register838
- USB Data Fifos838
- Figure 307. Updating OTG_FS_HFIR Dynamically838
- Peripheral FIFO Architecture839
- Host FIFO Architecture840
- FIFO RAM Allocation841
  - Device Mode841
  - Host Mode842
- USB System Performance842
- OTG_FS Interrupts843
- OTG_FS Control and Status Registers844
- OTG_FS Programming Model912
Ethernet (ETH): Media Access Control (MAC) with DMA Controller958
- Ethernet Introduction958
- Ethernet Main Features958
  - MAC Core Features959
  - DMA Features960
  - PTP Features960
- Ethernet Pins961
- Table 208. Ethernet Pin Configuration961
- Ethernet Functional Description: SMI, MII and RMII962
  - Station Management Interface: SMI962
  - Figure 326. ETH Block Diagram962
  - Table 209. Management Frame Format963
  - Figure 327. SMI Interface Signals963
  - Figure 328. MDIO Timing and Frame Structure - Write Cycle964
  - Table 210. Clock Range965
  - Figure 329. MDIO Timing and Frame Structure - Read Cycle965
- Media-Independent Interface: MII966
- Figure 330. Media Independent Interface Signals966
- Table 211. TX Interface Signal Encoding967
- Table 212. RX Interface Signal Encoding967
- Reduced Media-Independent Interface: RMII968
- Figure 331. MII Clock Sources968
- Figure 332. Reduced Media-Independent Interface Signals968
- MII/RMII Selection969
- Figure 333. RMII Clock Sources969
- Figure 334. Clock Scheme969
- Ethernet Functional Description: MAC 802.3970
  - MAC 802.3 Frame Format970
  - Figure 335. Address Field Format971
  - Figure 336. MAC Frame Format973
  - Figure 337. Tagged MAC Frame Format973
  - MAC Frame Transmission974
  - Figure 338. Transmission Bit Order980
  - Figure 339. Transmission with no Collision980
  - MAC Frame Reception981
  - Figure 340. Transmission with Collision981
  - Figure 341. Frame Transmission in MMI and RMII Modes981
  - Table 213. Frame Statuses983
  - Figure 342. Receive Bit Order985
  - Figure 343. Reception with no Error986
  - Figure 344. Reception with Errors986
  - Figure 345. Reception with False Carrier Indication986
  - MAC Interrupts987
  - MAC Filtering987
  - Figure 346. MAC Core Interrupt Masking Scheme987
  - Table 214. Destination Address Filtering989
  - MAC Loopback Mode990
  - MAC Management Counters: MMC990
  - Table 215. Source Address Filtering990
  - Power Management: PMT991
  - Figure 347. Wakeup Frame Filter Register992
  - Precision Time Protocol (IEEE1588 PTP)994
  - Figure 348. Networked Time Synchronization995
  - Figure 349. System Time Update Using the Fine Correction Method997
  - Figure 350. PTP Trigger Output to TIM2 ITR1 Connection999
- Ethernet Functional Description: DMA Controller Operation1000
  - Figure 351. PPS Output1000
  - Figure 352. Descriptor Ring and Chain Structure1001
  - Host Bus Burst Access1001
  - Initialization of a Transfer Using DMA1001
  - Buffer Size Calculations1002
  - Host Data Buffer Alignment1002
  - DMA Arbiter1003
  - Error Response to DMA1003
  - Tx DMA Configuration1003
  - Figure 353. Txdma Operation in Default Mode1005
  - Figure 354. Txdma Operation in OSF Mode1007
  - Figure 355. Ransmit Descriptor1008
  - Rx DMA Configuration1012
  - Figure 356. Receive DMA Operation1014
  - Figure 357. Rx DMA Descriptor Structure1016
  - Table 216. Receive Descriptor 01018
  - DMA Interrupts1020
- Ethernet Interrupts1021
- Figure 358. Interrupt Scheme1021
- Ethernet Register Descriptions1022
  - MAC Register Description1022
  - Figure 359. Ethernet MAC Remote Wakeup Frame Filter Register (ETH_MACRWUFFR)1031
  - MMC Register Description1039
  - IEEE 1588 Time Stamp Registers1044
  - DMA Register Description1048
  - Ethernet Register Maps1061
  - Table 217. Ethernet Register Map and Reset Values1062
Device Electronic Signature1065
- Memory Size Registers1065
  - Flash Size Register1065
- Unique Device ID Register (96 Bits)1066
Debug Support (DBG)1068
- Overview1068
- Reference ARM® Documentation1070
- SWJ Debug Port (Serial Wire and JTAG)1070
  - Figure 361. SWJ Debug Port1070
  - Mechanism to Select the JTAG-DP or the SW-DP1071
- Pinout and Debug Port Pins1071
- Stm32F10Xxx JTAG TAP Connection1074
- Figure 362. JTAG TAP Connections1075
- ID Codes and Locking Mechanism1076
- JTAG Debug Port1078
- Table 220. JTAG Debug Port Data Registers1078
- SW Debug Port1080
- AHB-AP (AHB Access Port) - Valid for both JTAG-DP and SW-DP1084
- Table 226. Cortex1084
- Core Debug1085
- Table 227. Core Debug Registers1085
- Capability of the Debugger Host to Connect under System Reset1086
- FPB (Flash Patch Breakpoint)1086
- DWT (Data Watchpoint Trigger)1087
- ITM (Instrumentation Trace Macrocell)1087
- ETM (Embedded Trace Macrocell)1089
Revision History1101
- Table 235. Document Revision History1101
- Figure 360. Block Diagram of STM32 MCU and Cortex ® -M3-Level1110

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