RCC_PLLCLK : defines the ADC clock divider. This clock is
derived from the PLL Clock. This parameter can be one of the
following values:
RCC_ADC12PLLCLK_OFF : ADC12 clock disabled
RCC_ADC12PLLCLK_Div1 : ADC12 clock = PLLCLK/1
RCC_ADC12PLLCLK_Div2 : ADC12 clock = PLLCLK/2
RCC_ADC12PLLCLK_Div4 : ADC12 clock = PLLCLK/4
RCC_ADC12PLLCLK_Div6 : ADC12 clock = PLLCLK/6
RCC_ADC12PLLCLK_Div8 : ADC12 clock = PLLCLK/8
RCC_ADC12PLLCLK_Div10 : ADC12 clock =
PLLCLK/10
RCC_ADC12PLLCLK_Div12 : ADC12 clock =
PLLCLK/12
RCC_ADC12PLLCLK_Div16 : ADC12 clock =
PLLCLK/16
RCC_ADC12PLLCLK_Div32 : ADC12 clock =
PLLCLK/32
RCC_ADC12PLLCLK_Div64 : ADC12 clock =
PLLCLK/64
RCC_ADC12PLLCLK_Div128 : ADC12 clock =
PLLCLK/128
RCC_ADC12PLLCLK_Div256 : ADC12 clock =
PLLCLK/256
RCC_ADC34PLLCLK_OFF : ADC34 clock disabled
RCC_ADC34PLLCLK_Div1 : ADC34 clock = PLLCLK/1
RCC_ADC34PLLCLK_Div2 : ADC34 clock = PLLCLK/2
RCC_ADC34PLLCLK_Div4 : ADC34 clock = PLLCLK/4
RCC_ADC34PLLCLK_Div6 : ADC34 clock = PLLCLK/6
RCC_ADC34PLLCLK_Div8 : ADC34 clock = PLLCLK/8
RCC_ADC34PLLCLK_Div10 : ADC34 clock =
PLLCLK/10
RCC_ADC34PLLCLK_Div12 : ADC34 clock =
PLLCLK/12
RCC_ADC34PLLCLK_Div16 : ADC34 clock =
PLLCLK/16
RCC_ADC34PLLCLK_Div32 : ADC34 clock =
PLLCLK/32
RCC_ADC34PLLCLK_Div64 : ADC34 clock =
PLLCLK/64
RCC_ADC34PLLCLK_Div128 : ADC34 clock =
PLLCLK/128
RCC_ADC34PLLCLK_Div256 : ADC34 clock =
PLLCLK/256