Xilinx KCU116 - Page 53

KCU116 Board User Guide 53
UG1239 (v1.2) September 28, 2018 www.xilinx.com
Chapter3: Board Component Descriptions
Table 3-16 lists the connections between the codec and the XCKU5P FPGA U1.
All HDMI nets in this table except HDMI_INT are series resistor coupled.
Table3‐16: HDMI Codec U52 to XCKU5P FPGA U1 Connections
FPGA (U1) Pin
Schematic Net
Name
I/O Standard
ADV7511 U52
Pin Number Name
V21 HDMI_D0 LVCMOS18 88 D8
V22 HDMI_D1 LVCMOS18 87 D9
T22 HDMI_D2 LVCMOS18 86 D10
T23 HDMI_D3 LVCMOS18 85 D11
W19 HDMI_D4 LVCMOS18 84 D12
W20 HDMI_D5 LVCMOS18 83 D13
Y22 HDMI_D6 LVCMOS18 82 D14
Y23 HDMI_D7 LVCMOS18 81 D15
Y25 HDMI_D8 LVCMOS18 80 D16
Y26 HDMI_D9 LVCMOS18 78 D17
AA24 HDMI_D10 LVCMOS18 74 D18
AA25 HDMI_D11 LVCMOS18 73 D19
W25 HDMI_D12 LVCMOS18 72 D20
W26 HDMI_D13 LVCMOS18 71 D21
V23 HDMI_D14 LVCMOS18 70 D22
W23 HDMI_D15 LVCMOS18 69 D23
V24 HDMI_D16 LVCMOS18 68 D24
W24 HDMI_D17 LVCMOS18 67 D25
U20 HDMI_DE LVCMOS18 97 DE
T20 HDMI_SPDIF LVCMOS18 10 SPDIF
P20 HDMI_CLK LVCMOS18 79 CLK
U21 HDMI_VSYNC LVCMOS18 2 VSYNC
V19 HDMI_HSYNC LVCMOS18 98 HSYNC
U19 HDMI_SPDIF_OUT LVCMOS18 46 SPDIF_OUT
R26 HDMI_INT LVCMOS18 45 INT
Notes: All HDMI nets in this table, except HDMI_INT, are series resistor coupled.
Send Feedback