Xilinx KCU116 - Page 70

KCU116 Board User Guide 70
UG1239 (v1.2) September 28, 2018 www.xilinx.com
Chapter3: Board Component Descriptions
Table3‐23: J5 HPC FMC Section C/D Connections to FPGA U1
J5
Pin
Schematic Net Name
I/O
Standard
U1
FPGA
Pin
J5
Pin
Schematic Net Name
I/O
Standard
U1 FPGA
Pin
C2 FMC_HPC0_DP0_C2M_P F7 D1 VADJ_1V8_PGOOD(3)
C3 FMC_HPC0_DP0_C2M_N F6 D4 FMC_HPC0_GBTCLK0_M2C_P K7
C6 FMC_HPC0_DP0_M2C_P D2 D5 FMC_HPC0_GBTCLK0_M2C_N K6
C7 FMC_HPC0_DP0_M2C_N D1 D8 FMC_HPC0_LA01_CC_P LVDS AC19
C10 FMC_HPC0_LA06_P LVDS Y20 D9 FMC_HPC0_LA01_CC_N LVDS AD19
C11 FMC_HPC0_LA06_N LVDS Y21 D11 FMC_HPC0_LA05_P LVDS AA19
C14 FMC_HPC0_LA10_P LVDS AF18 D12 FMC_HPC0_LA05_N LVDS AB19
C15 FMC_HPC0_LA10_N LVDS AF19 D14 FMC_HPC0_LA09_P LVDS AC18
C18 FMC_HPC0_LA14_P LVDS AE22 D15 FMC_HPC0_LA09_N LVDS AD18
C19 FMC_HPC0_LA14_N LVDS AF22 D17 FMC_HPC0_LA13_P LVDS AD23
C22 FMC_HPC0_LA18_CC_P LVDS AA22 D18 FMC_HPC0_LA13_N LVDS AE23
C23 FMC_HPC0_LA18_CC_N LVDS AB22 D20 FMC_HPC0_LA17_CC_P LVDS AD21
C26 NC D21 FMC_HPC0_LA17_CC_N LVDS AE21
C27 NC D23 NC NA
C30 FMC_HPC0_IIC_SCL D24 NC NA
C31 FMC_HPC0_IIC_SDA D26 NC NA
C34 GA0 = 0 = GND D27 NC NA
C35 VCC12_SW D29 FMC_HPC0_TCK_BUF
C37 VCC12_SW D30 FPGA_TDO_FMC_TDI_BUF
C39 UTIL_3V3 D31 FMC_HPC0_TDO
D32 UTIL_3V3
D33 FMC_HPC0_TMS_BUF
D34 NC
D35 GA1 = 0 = GND
D36 UTIL_3V3
D38 UTIL_3V3
D40 UTIL_3V3
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