Xilinx KCU116 - Page 73

KCU116 Board User Guide 73
UG1239 (v1.2) September 28, 2018 www.xilinx.com
Chapter3: Board Component Descriptions
Table3‐26: J5 HPC FMC Section J/K Connections to FPGA U1
J5
Pin
Schematic Net
Name
I/O Standard
U1 FPGA
Pin
J5 Pin
Schematic Net
Name
I/O Standard
U1 FPGA
Pin
J2 NC NA NA K1 NC NA NA
J3 NC NA NA K4 NC NA NA
J6 NC NA NA K5 NC NA NA
J7 NC NA NA K7 NC NA NA
J9 NC NA NA K8 NC NA NA
J10 NC NA N A K10 N C N A NA
J12 NC NA N A K11 N C N A NA
J13 NC NA N A K13 N C N A NA
J15 NC NA N A K14 N C N A NA
J16 NC NA N A K16 N C N A NA
J18 NC NA N A K17 N C N A NA
J19 NC NA N A K19 N C N A NA
J21 NC NA N A K20 N C N A NA
J22 NC NA N A K22 N C N A NA
J24 NC NA N A K23 N C N A NA
J25 NC NA N A K25 N C N A NA
J27 NC NA N A K26 N C N A NA
J28 NC NA N A K28 N C N A NA
J30 NC NA N A K29 N C N A NA
J31 NC NA N A K31 N C N A NA
J33 NC NA N A K32 N C N A NA
J34 NC NA N A K34 N C N A NA
J36 NC NA N A K35 N C N A NA
J37 NC NA N A K37 N C N A NA
J39 NC NA N A K38 N C N A NA
J39 NC NA N A K40 N C N A NA
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