Abov MC96F6332D User Manual

MC96F6432
June 22, 2018 Ver. 2.9 121
WTCR (Watch Timer Control Register) : 96H
7
6
5
4
3
2
1
0
WTEN
–
–
WTIFR
WTIN1
WTIN0
WTCK1
WTCK0
R/W
–
–
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
WTEN
Control Watch Timer
0
Disable
1
Enable
WTIFR
When WT Interrupt occurs, this bit becomes ‘1’. For clearing bit,
write ‘0’ to this bit or automatically clear by INT_ACK signal. Writing
“1” has no effect.
0
WT Interrupt no generation
1
WT Interrupt generation
WTIN[1:0]
Determine interrupt interval
WTIN1
WTIN0
Description
0
0
f
WCK
/2^7
0
1
f
WCK
/2^13
1
0
f
WCK
/2^14
1
1
f
WCK
/(2^14 x (7bit WTDR Value+1))
WTCK[1:0]
Determine Source Clock
WTCK1
WTCK0
Description
0
0
f
SUB
0
1
f
X
/256
1
0
f
X
/128
1
1
f
X
/64
NOTE) f
X
– System clock frequency (Where fx= 4.19MHz)
f
SUB
– Sub clock oscillator frequency (32.768kHz)
f
WCK
– Selected Watch timer clock
f
LCD
– LCD frequency (Where f
X
= 4.19MHz, WTCK[1:0]=’10’; f
LCD
= 1024Hz)

Abov MC96F6332D Specifications

General

Brand	Abov
Model	MC96F6332D
Category	Microcontrollers
Language	English