Abov MC96F6332D User Manual

MC96F6432
120 June 22, 2018 Ver. 2.9
11.4.3 Register Map
Table 11-4 Watch Timer Register Map
Name
Address
Dir
Default
Description
WTCNT
89H
R
00H
Watch Timer Counter Register
WTDR
89H
W
7FH
Watch Timer Data Register
WTCR
96H
R/W
00H
Watch Timer Control Register
11.4.4 Watch Timer Register Description
The watch timer register consists of watch timer counter register (WTCNT), watch timer data register (WTDR),
and watch timer control register (WTCR). As WTCR is 6-bit writable/ readable register, WTCR can control the
clock source (WTCK[1:0]), interrupt interval (WTIN[1:0]), and function enable/disable (WTEN). Also there is WT
interrupt flag bit (WTIFR).
11.4.5 Register Description for Watch Timer
WTCNT (Watch Timer Counter Register: Read Case) : 89H
7
6
5
4
3
2
1
0
–
WTCNT 6
WTCNT 5
WTCNT 4
WTCNT 3
WTCNT 2
WTCNT 1
WTCNT0
–
R
R
R
R
R
R
R
Initial value : 00H
WTCNT[6:0]
WT Counter
WTDR (Watch Timer Data Register: Write Case) : 89H
7
6
5
4
3
2
1
0
WTCL
WTDR 6
WTDR 5
WTDR 4
WTDR 3
WTDR 2
WTDR 1
WTDR 0
R/W
W
W
W
W
W
W
W
Initial value : 7FH
WTCL
Clear WT Counter
0
Free Run
1
Clear WT Counter (auto clear after 1 Cycle)
WTDR[6:0]
Set WT period
WT Interrupt Interval=fwck/(2^14 x(7bit WTDR Value+1))
NOTE) Do not write “0” in the WTDR register.

Abov MC96F6332D Specifications

General

Brand	Abov
Model	MC96F6332D
Category	Microcontrollers
Language	English