Abov MC96F6332D - Start and Stop Condition; Acknowledge Bit

MC96F6432
300 June 22, 2018 Ver. 2.9
14.2.2.3 Start and Stop Condition
Figure 14.5 Start and Stop Condition
14.2.2.4 Acknowledge Bit
Figure 14.6 Acknowledge on the Serial Bus
1
9
2
10
Data output
by transmitter
Data output
By receiver
DSCL from
master
clock pulse for acknowledgement
no acknowledge
acknowledge
St
Sp
START condition
STOP condition
DSDA
DSCL
DSDA
DSCL