Abov MC96F6332D - Effective Timing after Controlling Interrupt Bit; Figure 10.4 Effective Timing of Interrupt Enable Register; Figure 10.5 Effective Timing of Interrupt Flag Register

MC96F6432
98 June 22, 2018 Ver. 2.9
10.6 Effective Timing after Controlling Interrupt Bit
Case a) Control Interrupt Enable Register (IE, IE1, IE2, IE3)
Figure 10.4 Effective Timing of Interrupt Enable Register
Case b) Interrupt flag Register
Figure 10.5 Effective Timing of Interrupt Flag Register
Interrupt Flag Register
Command
Next Instruction
Next Instruction
After executing next instruction,
interrupt flag result is effective.
Interrupt Enable Register
command
Next Instruction
Next Instruction
After executing IE set/clear, enable
register is effective.