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MC96F6332D
Abov MC96F6332D User Manual
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MC96F6432
June 22,
20
18 Ver. 2.9
63
8.4 SFR M
ap
8.4.1 SFR Map
Summary
Table 8-1 SFR Map Summary
00H/8H
(1)
01H/9H
02H/0AH
03H/0BH
04H/0CH
05H/0DH
06H/0EH
07H/0FH
0F8H
IP1
–
FSADRH
FSADRM
FSADRL
FIDR
FMCR
P5FSR
0F0H
B
USI1ST1
USI1ST2
USI1BD
USI1SDHR
USI1DR
USI1SCLR
USI1SCHR
0E8H
RSTFR
USI1CR1
USI1CR2
USI1CR3
USI1CR4
USI1SAR
P3FSR
P4FSR
0E0H
ACC
USI0ST1
USI0ST2
USI0BD
USI0SDHR
USI0DR
USI0SCLR
USI0SCHR
0D8H
LVRCR
USI0CR1
USI0CR2
USI0CR3
USI0CR4
USI0SAR
P0DB
P15DB
0D0H
PSW
P5
IO
P0FSRL
P0FSRH
P1FSRL
P1FSRH
P2FSRL
P2FSRH
0C8H
OSCCR
P4
IO
–
–
–
–
–
–
0C0H
EIFLAG0
P3IO
T2CRL
T2CRH
T2ADRL
T2ADRH
T2BDRL
T2BDRH
0B8H
IP
P2
IO
T1CRL
T1CRH
T1ADRL
T1ADRH
T1BDRL
T1BDRH
0B0H
P5
P1
IO
T0CR
T0CNT
T0DR/
T0CDR
SPICR
SPIDR
SP
IS
R
0A8H
IE
IE1
IE2
IE3
P0PU
P1PU
P2PU
P3PU
0A0H
P4
P0
IO
EO
P4PU
EIPOL0L
EIPOL0H
EIFLAG1
EIPOL1
98H
P3
LCDCRL
LCDCRH
LCDCCR
ADCC
RH
ADCCRH
ADCDRL
ADCDRH
90H
P2
P0OD
P1
OD
P2
OD
P4
OD
P5PU
W
TCR
BUZCR
88H
P1
W
TDR/
W
TCNT
SC
CR
BITCR
BITCNT
W
DTCR
W
DTDR/
W
DTCNT
BUZDR
80H
P0
SP
DPL
DPH
DPL1
DPH1
LVICR
PCON
NOTE) 1. 00H/8H(1), These registers are bit-addressable.
2. Do not use the
“
direct bit test and branch
”
instruction on P0, P1, P2, P3, P4, P5 and EIFLAG0
re
gisters.
More detail information is at Appendix B.
Example) Avoid direct input port bit test and bran
ch condition as below
If(P00)
→
if(P0 & 0x01)
-
Reserved
M8051 com
patible
62
64
Table of Contents
Default Chapter
5
Table of Contents
5
1 Overview
13
Description
13
Features
14
Ordering Information
15
Table 1-1 Ordering Information of MC96F6432
15
Development Tools
16
Figure 1.1 Debugger(OCD1/OCD2) and Pin Description
16
Figure 1.2 E-PGM+(Single Writer)
17
Figure 1.3 E-GANG4 and E-GANG6 (for Mass Production)
18
2 Block Diagram
19
Figure 2.1 Block Diagram
19
3 Pin Assignment
20
Figure 3.1 MC96F6432L 48LQFP-0707 Pin Assignment
20
Figure 3.2 MC96F6432Q 44MQFP-1010 Pin Assignment
21
Figure 3.3 MC96F6332L 32LQFP Pin Assignment
22
Figure 3.4 MC96F6332D 32SOP Pin Assignment
23
Figure 3.5 MC96F6332M 28SOP Pin Assignment
23
4 Package Diagram
24
Figure 4.1 48-Pin LQFP-0707 Package
24
Figure 4.2 44-Pin MQFP Package
25
Figure 4.3 32-Pin LQFP Package
26
Figure 4.4 32-Pin SOP Package
27
Figure 4.5 28-Pin SOP Package
28
5 Pin Description
29
Table 5-1 Normal Pin Description
29
6 Port Structures
34
General Purpose I/O Port
34
Figure 6.1 General Purpose I/O Port
34
External Interrupt I/O Port
35
Figure 6.2 External Interrupt I/O Port
35
7 Electrical Characteristics
36
Absolute Maximum Ratings
36
Recommended Operating Conditions
36
Table 7-1 Absolute Maximum Ratings
36
Table 7-2 Recommended Operating Conditions
36
A/D Converter Characteristics
37
Power-On Reset Characteristics
37
Table 7-3 A/D Converter Characteristics
37
Table 7-4 Power-On Reset Characteristics
37
Low Voltage Reset and Low Voltage Indicator Characteristics
38
Table 7-5 LVR and LVI Characteristics
38
High Internal RC Oscillator Characteristics
39
Internal Watch-Dog Timer RC Oscillator Characteristics
39
Table 7-6 High Internal RC Oscillator Characteristics
39
Table 7-7 Internal WDTRC Oscillator Characteristics
39
LCD Voltage Characteristics
40
Table 7-8 LCD Voltage Characteristics
40
DC Characteristics
41
Table 7-9 DC Characteristics
41
AC Characteristics
43
Figure 7.1 AC Timing
43
Table 7-10 AC Characteristics
43
SPI0/1/2 Characteristics
44
Figure 7.2 SPI0/1/2 Timing
44
Table 7-11 SPI0/1/2 Characteristics
44
UART0/1 Characteristics
45
Figure 7.3 Waveform for UART0/1 Timing Characteristics
45
Figure 7.4 Timing Waveform for the UART0/1 Module
45
Table 7-12 UART0/1 Characteristics
45
I2C0/1 Characteristics
46
Figure 7.5 I2C0/1 Timing
46
Table 7-13 I2C0/1 Characteristics
46
Data Retention Voltage in Stop Mode
47
Figure 7.6 Stop Mode Release Timing When Initiated by an Interrupt
47
Figure 7.7 Stop Mode Release Timing When Initiated by RESETB
47
Table 7-14 Data Retention Voltage in Stop Mode
47
Internal Flash Rom Characteristics
48
Input/Output Capacitance
48
Table 7-15 Internal Flash Rom Characteristics
48
Table 7-16 Input/Output Capacitance
48
Main Clock Oscillator Characteristics
49
Figure 7.8 Crystal/Ceramic Oscillator
49
Figure 7.9 External Clock
49
Table 7-17 Main Clock Oscillator Characteristics
49
Sub Clock Oscillator Characteristics
50
Figure 7.10 Crystal Oscillator
50
Figure 7.11 External Clock
50
Table 7-18 Sub Clock Oscillator Characteristics
50
Main Oscillation Stabilization Characteristics
51
Sub Oscillation Characteristics
51
Figure 7.12 Clock Timing Measurement at XIN
51
Figure 7.13 Clock Timing Measurement at SXIN
51
Table 7-19 Main Oscillation Stabilization Characteristics
51
Table 7-20 Sub Oscillation Stabilization Characteristics
51
Operating Voltage Range
52
Figure 7.14 Operating Voltage Range
52
Recommended Circuit and Layout
53
Figure 7.15 Recommended Circuit and Layout
53
Recommended Circuit and Layout with SMPS Power
54
Figure 7.16 Recommended Circuit and Layout with SMPS Power
54
Typical Characteristics
55
Figure 7.17 RUN (IDD1 ) Current
55
Figure 7.18 IDLE (IDD2) Current
55
Figure 7.19 SUB RUN (IDD3) Current
56
Figure 7.20 SUB IDLE (IDD4) Current
56
Figure 7.21 STOP (IDD5) Current
57
8 Memory
58
Program Memory
58
Figure 8.1 Program Memory
59
Data Memory
60
Figure 8.2 Data Memory Map
60
Figure 8.3 Lower 128 Bytes RAM
61
XRAM Memory
62
Figure 8.4 XDATA Memory Area
62
SFR Map
63
Table 8-1 SFR Map Summary
63
Table 8-2 SFR Map Summary
64
Table 8-3 SFR Map
65
9 I/O Ports
72
Port Register
72
Table 9-1 Port Register Map
73
P0 Port
74
P1 Port
76
P2 Port
78
P3 Port
80
P4 Port
81
P5 Port
83
Port Function
84
10 Interrupt Controller
93
Overview
93
Table 10-1 Interrupt Group Priority Level
93
External Interrupt
94
Figure 10.1 External Interrupt Description
94
Block Diagram
95
Figure 10.2 Block Diagram of Interrupt
95
Interrupt Vector Table
96
Interrupt Sequence
96
Table 10-2 Interrupt Vector Address Table
96
Figure 10.3 Interrupt Sequence Flow
97
Effective Timing after Controlling Interrupt Bit
98
Figure 10.4 Effective Timing of Interrupt Enable Register
98
Figure 10.5 Effective Timing of Interrupt Flag Register
98
Multi Interrupt
99
Figure 10.6 Effective Timing of Multi-Interrupt
99
Interrupt Enable Accept Timing
100
Interrupt Service Routine Address
100
Saving/Restore General-Purpose Registers
100
Figure 10.7 Interrupt Response Timing Diagram
100
Figure 10.8 Correspondence between Vector Table Address and the Entry Address of ISR
100
Figure 10.9 Saving/Restore Process Diagram and Sample Source
100
Interrupt Timing
101
Interrupt Register Overview
101
Figure 10.10 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction
101
Table 10-3 Interrupt Register Map
103
11 Peripheral Hardware
110
Clock Generator
110
Figure 11.1 Clock Generator Block Diagram
110
Table 11-1 Clock Generator Register Map
111
Basic Interval Timer
113
Figure 11.2 Basic Interval Timer Block Diagram
113
Table 11-2 Basic Interval Timer Register Map
114
Watch Dog Timer
116
Figure 11.3 Watch Dog Timer Interrupt Timing Waveform
116
Figure 11.4 Watch Dog Timer Block Diagram
117
Table 11-3 Watch Dog Timer Register Map
117
Watch Timer
119
Figure 11.5 Watch Timer Block Diagram
119
Table 11-4 Watch Timer Register Map
120
Timer 0
122
Table 11-5 Timer 0 Operating Modes
122
Figure 11.6 8-Bit Timer/Counter Mode for Timer 0
123
Figure 11.7 8-Bit Timer/Counter 0 Example
123
Figure 11.8 8-Bit PWM Mode for Timer 0
124
Figure 11.9 PWM Output Waveforms in PWM Mode for Timer 0
125
Figure 11.10 8-Bit Capture Mode for Timer 0
126
Figure 11.11 Input Capture Mode Operation for Timer 0
127
Figure 11.12 Express Timer Overflow in Capture Mode
127
Figure 11.13 8-Bit Timer 0 Block Diagram
128
Table 11-6 Timer 0 Register Map
129
Timer 1
131
Table 11-7 Timer 1 Operating Modes
131
Figure 11.14 16-Bit Timer/Counter Mode for Timer 1
132
Figure 11.15 16-Bit Timer/Counter 1 Example
132
Figure 11.16 16-Bit Capture Mode for Timer 1
133
Figure 11.17 Input Capture Mode Operation for Timer 1
134
Figure 11.18 Express Timer Overflow in Capture Mode
134
Figure 11.19 16-Bit PPG Mode for Timer 1
135
Figure 11.20 16-Bit PPG Mode Timming Chart for Timer 1
136
Figure 11.21 16-Bit Timer 1 Block Diagram
137
Table 11-8 Timer 2 Register Map
137
Timer 2
141
Table 11-9 Timer 2 Operating Modes
141
Figure 11.22 16-Bit Timer/Counter Mode for Timer 2
142
Figure 11.23 16-Bit Timer/Counter 2 Example
143
Figure 11.24 16-Bit Capture Mode for Timer 2
144
Figure 11.25 Input Capture Mode Operation for Timer 2
145
Figure 11.26 Express Timer Overflow in Capture Mode
145
Figure 11.27 16-Bit PPG Mode for Timer 2
146
Figure 11.28 16-Bit PPG Mode Timming Chart for Timer 2
147
Figure 11.29 16-Bit Timer 2 Block Diagram
148
Table 11-10 Timer 3 Register Map
148
Timer 3, 4
152
Table 11-11 Timer 3, 4 Operating Modes
152
Figure 11.30 8-Bit Timer/Counter Mode for Timer 3, 4
153
Figure 11.31 16-Bit Timer/Counter Mode for Timer 3
154
Figure 11.32 8-Bit Capture Mode for Timer 3, 4
156
Figure 11.33 16-Bit Capture Mode for Timer 3
157
Table 11-12 PWM Frequency Vs. Resolution at 8 Mhz
158
Table 11-13 PWM Channel Polarity
158
Figure 11.34 10-Bit PWM Mode (Force 6-Ch)
159
Figure 11.35 10-Bit PWM Mode (Force All-Ch)
160
Figure 11.36 Example of PWM at 4 Mhz
161
Figure 11.37 Example of Changing the Period in Absolute Duty Cycle at 4 Mhz
161
Figure 11.38 Example of PWM Output Waveform
162
Figure 11.39 Example of PWM Waveform in Back-To-Back Mode at 4 Mhz
162
Figure 11.40 Example of Phase Correction and Frequency Correction of PWM
163
Figure 11.41 Example of PWM External Synchronization with BLNK Input
163
Figure 11.42 Example of Force Drive All Channel with A-Ch
164
Figure 11.43 Example of Force Drive 6-Ch Mode
165
Figure 11.44 Example of PWM Delay
167
Figure 11.45 Two 8-Bit Timer 3, 4 Block Diagram
168
Figure 11.46 16-Bit Timer 3 Block Diagram
169
Figure 11.47 10-Bit PWM Timer 4 Block Diagram
169
Table 11-14 Timer 3, 4 Register Map
170
Buzzer Driver
181
Figure 11.48 Buzzer Driver Block Diagram
181
Table 11-15 Buzzer Frequency at 8 Mhz
181
Table 11-16 Buzzer Driver Register Map
182
Spi 2
183
Figure 11.49 SPI 2 Block Diagram
183
Figure 11.50 SPI 2 Transmit/Receive Timing Diagram at CPHA = 0
185
Figure 11.51 SPI 2 Transmit/Receive Timing Diagram at CPHA = 1
185
Table 11-17 SPI 2 Register Map
186
12-Bit A/D Converter
189
Figure 11.52 12-Bit ADC Block Diagram
190
Figure 11.53 A/D Analog Input Pin with Capacitor
190
Figure 11.54 A/D Power (AVREF) Pin with Capacitor
190
Figure 11.55 ADC Operation for Align Bit
191
Figure 11.56 A/D Converter Operation Flow
192
Table 11-18 ADC Register Map
192
Usi0 (Uart + Spi + I2C)
195
Figure 11.57 USI0 UART Block Diagram
197
Figure 11.58 Clock Generation Block Diagram (USI0)
198
Table 11-19 Equations for Calculating USI0 Baud Rate Register Setting
198
Figure 11.59 Synchronous Mode SCK0 Timing (USI0)
199
Figure 11.60 Frame Format (USI0)
200
Figure 11.61 Asynchronous Start Bit Sampling (USI0)
204
Figure 11.62 Asynchronous Sampling of Data and Parity Bit (USI0)
204
Figure 11.63 Stop Bit Sampling and Next Start Bit Sampling (USI0)
205
Table 11-20 CPOL0 Functionality
206
Figure 11.64 USI0 SPI Clock Formats When CPHA0=0
207
Figure 11.65 USI0 SPI Clock Formats When CPHA0=1
208
Figure 11.66 USI0 SPI Block Diagram
209
Figure 11.67 Bit Transfer on the I2C-Bus (USI0)
210
Figure 11.68 START and STOP Condition (USI0)
211
Figure 11.69 Data Transfer on the I2C-Bus (USI0)
211
Figure 11.70 Acknowledge on the I2C-Bus (USI0)
212
Figure 11.71 Clock Synchronization During Arbitration Procedure (USI0)
213
Figure 11.72 Arbitration Procedure of Two Masters (USI0)
213
Figure 11.73 Formats and States in the Master Transmitter Mode (USI0)
215
Figure 11.74 Formats and States in the Master Receiver Mode (USI0)
217
Figure 11.75 Formats and States in the Slave Transmitter Mode (USI0)
219
Figure 11.76 Formats and States in the Slave Receiver Mode (USI0)
221
Figure 11.77 USI0 I2C Block Diagram
222
Table 11-21 USI0 Register Map
223
Usi1 (Uart + Spi + I2C)
232
Figure 11.78 USI1 UART Block Diagram
234
Figure 11.79 Clock Generation Block Diagram (USI1)
235
Table 11-22 Equations for Calculating USI1 Baud Rate Register Setting
235
Figure 11.80 Synchronous Mode SCK1 Timing (USI1)
236
Figure 11.81 Frame Format (USI1)
237
Figure 11.82 Asynchronous Start Bit Sampling (USI1)
241
Figure 11.83 Asynchronous Sampling of Data and Parity Bit (USI1)
241
Figure 11.84 Stop Bit Sampling and Next Start Bit Sampling (USI1)
242
Table 11-23 CPOL1 Functionality
243
Figure 11.85 USI1 SPI Clock Formats When CPHA1=0
244
Figure 11.86 USI1 SPI Clock Formats When CPHA1=1
245
Figure 11.87 USI1 SPI Block Diagram
246
Figure 11.88 Bit Transfer on the I2C-Bus (USI1)
247
Figure 11.89 START and STOP Condition (USI1)
248
Figure 11.90 Data Transfer on the I2C-Bus (USI1)
248
Figure 11.91 Acknowledge on the I2C-Bus (USI1)
249
Figure 11.92 Clock Synchronization During Arbitration Procedure (USI1)
250
Figure 11.93 Arbitration Procedure of Two Masters (USI1)
250
Figure 11.94 Formats and States in the Master Transmitter Mode (USI1)
252
Figure 11.95 Formats and States in the Master Receiver Mode (USI1)
254
Figure 11.96 Formats and States in the Slave Transmitter Mode (USI1)
256
Figure 11.97 Formats and States in the Slave Receiver Mode (USI1)
258
Figure 11.98 USI1 I2C Block Diagram
259
Table 11-24 USI1 Register Map
260
Table 11-25 Examples of USI0BD and USI1BD Settings for Commonly Used Oscillator Frequencies
269
LCD Driver
270
Figure 11.99 LCD Circuit Block Diagram
271
Figure 11.100 LCD Signal Waveforms (1/2Duty, 1/2Bias)
272
Figure 11.101 LCD Signal Waveforms (1/3Duty, 1/3Bias)
273
Figure 11.102 LCD Signal Waveforms (1/4Duty, 1/3Bias)
274
Figure 11.103 LCD Signal Waveforms (1/8Duty, 1/4Bias)
275
Figure 11.104 Internal Resistor Bias Connection
276
Figure 11.105 External Resistor Bias Connection
277
Figure 11.106 LCD Circuit Block Diagram
278
Table 11-26 LCD Register Map
278
Table 11-27 LCD Frame Frequency
280
12 Power down Operation
282
Overview
282
Peripheral Operation in IDLE/STOP Mode
282
Table 12-1 Peripheral Operation During Power down Mode
282
IDLE Mode
283
Figure 12.1 IDLE Mode Release Timing by External Interrupt
283
STOP Mode
284
Figure 12.2 STOP Mode Release Timing by External Interrupt
284
Release Operation of STOP Mode
285
Figure 12.3 STOP Mode Release Flow
285
Table 12-2 Power down Operation Register Map
286
13 Reset
287
Overview
287
Reset Source
287
RESET Block Diagram
287
Figure 13.1 RESET Block Diagram
287
Table 13-1 Reset State
287
RESET Noise Canceller
288
Power on RESET
288
Figure 13.2 Reset Noise Canceller Timer Diagram
288
Figure 13.3 Fast VDD Rising Time
288
Figure 13.4 Internal RESET Release Timing on Power-Up
288
Figure 13.5 Configuration Timing When Power-On
289
Figure 13.6 Boot Process Waveform
289
Table 13-2 Boot Process Description
290
External RESETB Input
291
Figure 13.7 Timing Diagram after RESET
291
Figure 13.8 Oscillator Generating Waveform Example
291
Brown out Detector Processor
292
Figure 13.9 Block Diagram of BOD
292
Figure 13.10 Internal Reset at the Power Fail Situation
292
LVI Block Diagram
293
Figure 13.11 Configuration Timing When BOD RESET
293
Figure 13.12 LVI Diagram
293
Register Map
294
Reset Operation Register Description
294
Register Description for Reset Operation
294
Table 13-3 Reset Operation Register Map
294
14 On-Chip Debug System
297
Overview
297
Figure 14.1 Block Diagram of On-Chip Debug System
297
Two-Pin External Interface
298
Figure 14.2 10-Bit Transmission Packet
298
Figure 14.3 Data Transfer on the Twin Bus
299
Figure 14.4 Bit Transfer on the Serial Bus
299
Figure 14.5 Start and Stop Condition
300
Figure 14.6 Acknowledge on the Serial Bus
300
Figure 14.7 Clock Synchronization During Wait Procedure
301
Figure 14.8 Connection of Transmission
302
15 Flash Memory
303
Overview
303
Figure 15.1 Flash Program ROM Structure
304
Table 15-1Flash Memory Register Map
305
Figure 15.2 Flow of Protection for Invalid Erase/Write
315
16 Configure Option
317
Configure Option Control
317
17 Appendix
318
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Abov MC96F6332D Specifications
General
Brand
Abov
Model
MC96F6332D
Category
Microcontrollers
Language
English
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