Abov MC96F6332D - USI0 SPI Block Diagram

MC96F6432
June 22, 2018 Ver. 2.9 209
11.12.13 USI0 SPI Block Diagram
RXCIE0
Rx Control
Receive Shift Register
(RXSR)
Data
Recovery
DOR0 Checker USI0DR[0], (Rx)
Tx Control
Transmit Shift Register
(TXSR)
USI0DR, (Tx)
I
N
T
E
R
N
A
L
B
U
S
L
I
N
E
M
U
X
LOOPS0
TXC0
TXCIE0 DRIE0
DRE0
Empty signal
To interrupt
block
INT_ACK
Clear
RXC0
Baud Rate Generator
USI0BD
TXE0
SCLK
(fx: System clock)
MISO0
MOSI0
M
U
X
MASTER0
D
E
P
FXCH0
SCK0
SCK
Control
MASTER0
RXE0
To interrupt
block
M
U
X
Edge Detector
And
Controller
SS0
SS
Control
CPHA0CPOL0
ORD0
(MSB/LSB-1st)
USI0DR[1], (Rx)
USI0SSEN
Figure 11.66 USI0 SPI Block Diagram