Abov MC96F6332D - Figure 11.87 USI1 SPI Block Diagram

MC96F6432
246 June 22, 2018 Ver. 2.9
11.13.13 USI1 SPI Block Diagram
RXCIE1
Rx Control
Receive Shift Register
(RXSR)
Data
Recovery
DOR1 Checker USI1DR[0], (Rx)
Tx Control
Transmit Shift Register
(TXSR)
USI1DR, (Tx)
I
N
T
E
R
N
A
L
B
U
S
L
I
N
E
M
U
X
LOOPS1
TXC1
TXCIE1 DRIE1
DRE1
Empty signal
To interrupt
block
INT_ACK
Clear
RXC1
Baud Rate Generator
USI1BD
TXE1
SCLK
(fx: System clock)
MISO1
MOSI1
M
U
X
MASTER1
D
E
P
FXCH1
SCK1
SCK
Control
MASTER1
RXE1
To interrupt
block
M
U
X
Edge Detector
And
Controller
SS1
SS
Control
CPHA1CPOL1
ORD1
(MSB/LSB-1st)
USI1DR[1], (Rx)
USI1SSEN
Figure 11.87 USI1 SPI Block Diagram