MC96F6432
244 June 22, 2018 Ver. 2.9
Figure 11.85 USI1 SPI Clock Formats when CPHA1=0
When CPHA1=0, the slave begins to drive its MISO1 output with the first data bit value when SS1 goes to active
low. The first SCK1 edge causes both the master and the slave to sample the data bit value on their MISO1 and
MOSI1 inputs, respectively. At the second SCK1 edge, the USI1 shifts the second data bit value out to the
MOSI1 and MISO1 outputs of the master and slave, respectively. Unlike the case of CPHA1=1, when CPHA1=0,
the slave’s SS1 input must go to its inactive high level between transfers. This is because the slave can prepare
the first data bit when it detects falling edge of SS1 input.
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