Abov MC96F6332D - Packet Transmission Timing

MC96F6432
June 22, 2018 Ver. 2.9 299
14.2.2 Packet Transmission Timing
14.2.2.1 Data Transfer
Figure 14.3 Data Transfer on the Twin Bus
14.2.2.2 Bit Transfer
Figure 14.4 Bit Transfer on the Serial Bus
data line
stable:
data valid
except Start and Stop
change
of data
allowed
DSDA
DSCL
St
Sp
START
STOP
DSDA
DSCL
LSB
acknowledgement
signal from receiver
ACK
ACK
1
10
1
10
acknowledgement
signal from receiver
LSB