MC96F6432
166 June 22, 2018 Ver. 2.9
PWM output Delay
If using the T4DLYA, T4DLYB, T4DLYC register, it can delay PWM output based on the rising edge. At that time,
it does not change the falling edge, so the duty is reduced as the time delay. In POLAA/BA/CA setting to ‘0’, the
delay is applied to the falling edge. In POLAA/BA/CA setting to ‘1’, the delay is applied to the rising edge. It can
produce a pair of Non-overlapping clock. The each channel is able to have 4-bit delay. As it can select the clock
up to 1/8 divided clock using NOPS[1:0] the delay of its maximum 128 timer clock cycle is produced.
To Next Page
Loading...
Need help?
General
