Abov MC96F6332D - T3 CR (Timer 3 Control Register)

MC96F6432
172 June 22, 2018 Ver. 2.9
T3CR (Timer 3 Control Register) : 1000H (ESFR)
7
6
5
4
3
2
1
0
T3EN
–
T3MS
T3CK2
T3CK1
T3CK0
T3CN
T3ST
R/W
–
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
T3EN
Control Timer 3
0
Timer 3 disable
1
Timer 3 enable
T3MS
Control Timer 3 Operation Mode
0
Timer/counter mode (T3O: toggle at match)
1
Capture mode (the match interrupt can occur)
T3CK[2:0]
Select Timer 3 clock source. fx is main system clock frequency
T3CK2
T3CK1
T3CK0
Description
0
0
0
fx/2
0
0
1
fx/4
0
1
0
fx/8
0
1
1
fx/32
1
0
0
fx/128
1
0
1
fx/512
1
1
0
fx/2048
1
1
1
External Clock (EC3)
T3CN
Control Timer 3 Count Pause/Continue
0
Temporary count stop
1
Continue count
T3ST
Control Timer 3 Start/Stop
0
Counter stop
1
Clear counter and start
NOTE) Refer to the external interrupt flag 1 register (EIFLAG1) for the T3 interrupt flag.