MC96F6432
224 June 22, 2018 Ver. 2.9
USI0DR (USI0 Data Register: For UART, SPI, and I2C mode) : E5H
Initial value : 00H
The USI0 transmit buffer and receive buffer share the same I/O
address with this DATA register. The transmit data buffer is the
destination for data written to the USI0DR register. Reading the
USI0DR register returns the contents of the receive buffer.
Write to this register only when the DRE0 flag is set. In SPI master
mode, the SCK clock is generated when data are written to this
register.
USI0SDHR (USI0 SDA Hold Time Register: For I2C mode) : E4H
Initial value : 01H
The register is used to control SDA0 output timing from the falling
edge of SCI in I2C mode.
NOTE) That SDA0 is changed after t
SCLK
X (USI0SDHR+2), in
master SDA 0 change in the middle of SCL0.
In slave mode, configure this register regarding the frequency of
SCL0 from master.
The SDA0 is changed after tsclk X (USI0SDHR+2) in master
mode. So, to insure operation in slave mode, the value
t
SCLK
X (USI0SDHR +2) must be smaller than the period of SCL.
USI0SCHR (USI0 SCL High Period Register: For I2C mode) : E7H
Initial value : 3FH
This register defines the high period of SCL0 when it operates in
I2C master mode.
The base clock is SCLK, the system clock, and the period is
calculated by the formula: t
SCLK
X (4 X USI0SCHR +2) where
t
SCLK
is the period of SCLK.
So, the operating frequency of I2C master mode is calculated by the following equation.
t
SCLK
X (4 X (USI0SCLR + USI0SCHR) + 4)