Abov MC96F6332D User Manual

MC96F6432
224 June 22, 2018 Ver. 2.9
USI0DR (USI0 Data Register: For UART, SPI, and I2C mode) : E5H
7
6
5
4
3
2
1
0
USI0DR7
USI0DR 6
USI0DR 5
USI0DR 4
USI0DR 3
USI0DR 2
USI0DR 1
USI0DR 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
USI0DR[7:0]
The USI0 transmit buffer and receive buffer share the same I/O
address with this DATA register. The transmit data buffer is the
destination for data written to the USI0DR register. Reading the
USI0DR register returns the contents of the receive buffer.
Write to this register only when the DRE0 flag is set. In SPI master
mode, the SCK clock is generated when data are written to this
register.
USI0SDHR (USI0 SDA Hold Time Register: For I2C mode) : E4H
7
6
5
4
3
2
1
0
USI0SDHR7
USI0SDHR6
USI0SDHR5
USI0SDHR 4
USI0SDHR 3
USI0SDHR 2
USI0SDHR 1
USI0SDHR 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 01H
USI0SDHR[7:0]
The register is used to control SDA0 output timing from the falling
edge of SCI in I2C mode.
NOTE) That SDA0 is changed after t
SCLK
X (USI0SDHR+2), in
master SDA 0 change in the middle of SCL0.
In slave mode, configure this register regarding the frequency of
SCL0 from master.
The SDA0 is changed after tsclk X (USI0SDHR+2) in master
mode. So, to insure operation in slave mode, the value
t
SCLK
X (USI0SDHR +2) must be smaller than the period of SCL.
USI0SCHR (USI0 SCL High Period Register: For I2C mode) : E7H
7
6
5
4
3
2
1
0
USI0SCHR7
USI0SCHR6
USI0SCHR5
USI0SCHR 4
USI0SCHR 3
USI0SCHR 2
USI0SCHR 1
USI0SCHR 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 3FH
USI0SCHR[7:0]
This register defines the high period of SCL0 when it operates in
I2C master mode.
The base clock is SCLK, the system clock, and the period is
calculated by the formula: t
SCLK
X (4 X USI0SCHR +2) where
t
SCLK
is the period of SCLK.
So, the operating frequency of I2C master mode is calculated by the following equation.
f
I2C
=
t
SCLK
X (4 X (USI0SCLR + USI0SCHR) + 4)
1

Abov MC96F6332D Specifications

General

Flash Memory	32 KB
PWM Channels	6
ADC Resolution	10-bit
UART	1
SPI	1
I2C	1
GPIO Pins	36
CPU Speed	16 MHz
Operating Temperature	-40°C to 85°C
Core	8-bit CISC core
Package	LQFP-48

Summary

Overview

Features

Block Diagram

Pin Assignment

Package Diagram

Pin Description

Normal Pin Description

Details the function and shared pins for each device pin.

Normal Pin Description (Continued)

Provides final notes on pin description.

Port Structures

General Purpose I/O Port

External Interrupt I/O Port

Electrical Characteristics

Absolute Maximum Ratings

Lists electrical parameters that should not be exceeded.

Recommended Operating Conditions

Specifies the voltage and temperature ranges for proper operation.

A/D Converter Characteristics

Power-On Reset Characteristics

Low Voltage Reset and Low Voltage Indicator Characteristics

DC Characteristics

Lists DC electrical parameters.

DC Characteristics (Continued)

Continues the DC electrical parameters.

AC Characteristics

Lists AC electrical parameters and timing diagrams.

SPI0/1/2 Characteristics

UART0/1 Characteristics

I2C0/1 Characteristics

Internal Flash Rom Characteristics

Main Clock Oscillator Characteristics

Sub Clock Oscillator Characteristics

Recommended Circuit and Layout

Provides recommended circuit diagrams and layout guidelines.

Recommended Circuit and Layout with SMPS Power

Offers guidance for circuits using SMPS power.

Memory

Program Memory

Shows the map of the program memory.

Data Memory

Describes the internal data memory space.

Lower 128 Bytes RAM

XRAM Memory

SFR Map Summary

Provides a summary of the Special Function Register map.

SFR Map Summary (Continued)

Continues the SFR map summary.

SFR Map (Continued)

Continues the SFR map.

I/O Ports

I/O Ports

Provides a general overview of the I/O ports.

Port Register Map

P0 Port

P1 Port

P2 Port

P3 Port

P4 Port

P5 Port

Port Function Description

Interrupt Controller

External Interrupt

Interrupt Vector Table

Lists all interrupt sources and their vector addresses.

Interrupt Sequence Flow

External Interrupt Flag Register (EIFLAG0, EIFLAG1)

External Interrupt Polarity Register (EIPOL0L, EIPOL0H, EIPOL1)

Register Description for Interrupt

IE1 (Interrupt Enable Register 1)

IE2 (Interrupt Enable Register 2)

IE3 (Interrupt Enable Register 3)

IP (Interrupt Priority Register)

Describes the IP register for interrupt priority.

IP1 (Interrupt Priority Register 1)

Describes the IP1 register for interrupt priority.

EIFLAG0 (External Interrupt Flag 0 Register)

EIPOL0H (External Interrupt Polarity 0 High Register)

EIPOL0L (External Interrupt Polarity 0 Low Register)

EIFLAG1 (External Interrupt Flag 1 Register)

EIPOL1 (External Interrupt Polarity 1 Register)

Peripheral Hardware

Clock Generator

Provides an overview of the clock generator.

Clock Generator Register Description

Describes clock generator registers.

Register Description for Clock Generator

OSCCR (Oscillator Control Register)

Basic Interval Timer

Provides an overview of the basic interval timer.

Basic Interval Timer Register Description

Register Description for Basic Interval Timer

Watch Dog Timer

Provides an overview of the watchdog timer.

Register Description for Watch Dog Timer

Details WDTCNT, WDTDR, and WDTCR registers.

Watch Timer

Provides an overview of the watch timer's functionality.

Watch Timer Register Description

Describes WTCNT, WTDR, and WTCR registers.

WTCR (Watch Timer Control Register)

Timer 0

Provides an overview of Timer 0.

8-Bit Timer/Counter Mode

Describes the 8-bit timer/counter mode for Timer 0.

8-Bit PWM Mode

Describes the 8-bit PWM mode for Timer 0.

8-Bit Capture Mode

Describes the 8-bit capture mode for Timer 0.

8-Bit Timer 0 Block Diagram

Shows the block diagram for Timer 0.

T0CR (Timer 0 Control Register)

Timer 1

Provides an overview of the 16-bit Timer 1 module.

16-Bit Timer/Counter Mode for Timer 1

Shows the block diagram for 16-bit timer/counter mode.

16-Bit PPG Mode Timming chart for Timer 1

Timer/Counter 1 Register Description

T1CRH (Timer 1 Control High Register)

T1CRL (Timer 1 Control Low Register)

Timer 2

Provides an overview of the 16-bit Timer 2 module.

16-Bit Timer/Counter Mode

Describes the 16-bit timer/counter mode for Timer 2.

16-Bit Capture Mode

Describes the 16-bit capture mode for Timer 2.

16-Bit PPG Mode

Describes the 16-bit PPG mode for Timer 2.

16-Bit PPG Mode Timming chart for Timer 2

Timer/Counter 2 Register Description

T2CRH (Timer 2 Control High Register)

T2CRL (Timer 2 Control Low Register)

Timer 3, 4

Provides an overview of the Timer 3 and Timer 4 modules.

8-Bit Timer/Counter 3, 4 Mode

Describes the 8-bit modes for Timers 3 and 4.

16-Bit Timer/Counter 3 Mode

Describes the 16-bit mode for Timer 3.

8-Bit Timer 3, 4 Capture Mode

Describes the 8-bit capture mode for Timers 3 and 4.

8-Bit Capture Mode for Timer 3, 4

Shows the block diagram for 8-bit capture mode.

16-Bit Timer 3 Capture Mode

Describes the 16-bit capture mode for Timer 3.

10-Bit Timer 4 PWM Mode

Describes the 10-bit PWM mode for Timer 4.

10-Bit PWM Mode (Force 6-ch)

10-Bit PWM Mode (Force All-ch)

Two 8-Bit Timer 3, 4 Block Diagram

Shows block diagram for 8-bit Timer 3/4.

16-Bit Timer 3 Block Diagram

10-Bit PWM Timer 4 Block Diagram

Timer/Counter 3 Register Description

T3CR (Timer 3 Control Register)

Timer/Counter 4 Register Description

Describes Timer 4 registers.

Timer 4 PWM B Duty High/Low Register

Timer 4 PWM C Duty High/Low Register

T4DR (Timer 4 Data Register)

T4CAPR (Timer 4 Capture Data Register)

T4CNT (Timer 4 Counter Register)

T4CR (Timer 4 Control Register)

Details the T4CR register.

T4PCR1 (Timer 4 PWM Control Register 1)

Details T4PCR1 register.

T4PCR2 (Timer 4 PWM Control Register 2)

Details T4PCR2 register.

T4PCR3 (Timer 4 PWM Control Register 3)

Details T4PCR3 register.

T4ISR (Timer 4 Interrupt Status Register)

T4MSK (Timer 4 Interrupt Mask Register)

Buzzer Driver

Provides an overview of the buzzer driver.

Buzzer Driver Register Description

Describes BUZDR and BUZCR registers.

SPI 2

Provides an overview of the SPI 2 interface.

Data Transmit / Receive Operation

SPI 2 Timing Diagram

SPI 2 Register Description

Describes SPI 2 registers.

SPISR (SPI 2 Status Register)

SPICR (SPI 2 Control Register)

Details the SPICR register.

12-Bit A/D Converter

Provides an overview of the 12-bit A/D converter.

ADC Operation

A/D Converter Operation Flow

Register Description for ADC

Describes ADCDRH, ADCDRL, ADCCRH registers.

ADCCRL (A/D Converter Control Low Register)

USI0 (UART + SPI + I2C)

Provides an overview of the USI0 module.

USI0 UART Mode

Describes the main features of the USI0 UART mode.

USI0 UART Block Diagram

Shows the block diagram for USI0 UART.

USI0 Clock Generation

Explains the clock generation for USI0.

Equations for Calculating USI0 Baud Rate Register Setting

USI0 Synchronous mode operation

USI0 UART Data format

USI0 UART Transmitter

Explains the UART transmitter.

USI0 UART Transmitter flag and interrupt

USI0 UART Receiver

Provides an overview of the UART receiver.

USI0 UART Receiver Flag and Interrupt

USI0 Asynchronous Data Reception

Explains asynchronous data reception.

Asynchronous Sampling of Data and Parity Bit (USI0)

Stop Bit Sampling and Next Start Bit Sampling (USI0)

USI0 SPI Mode

Describes the SPI mode features.

USI0 SPI Clock Formats and Timing

Explains SPI clock formats and timing.

USI0 SPI Clock Formats when CPHA0=1

USI0 SPI Block Diagram

Shows the block diagram for USI0 SPI.

USI0 I2C Mode

Describes the I2C mode features.

USI0 I2C Bit Transfer

START and STOP Condition (USI0)

USI0 I2C Data Transfer

Acknowledge on the I2C-Bus (USI0)

USI0 I2C Synchronization / Arbitration

USI0 I2C Operation

General description of I2C operation.

Formats and States in the Master Transmitter Mode (USI0)

USI0 I2C Master Receiver

Explains how to operate I2C in master receiver mode.

Formats and States in the Master Receiver Mode (USI0)

USI0 I2C Slave Transmitter

Explains how to operate I2C in slave transmitter mode.

Formats and States in the Slave Transmitter Mode (USI0)

USI0 I2C Slave Receiver

Explains how to operate I2C in slave receiver mode.

Formats and States in the Slave Receiver Mode (USI0)

USI0 I2C Block Diagram

Shows the block diagram for USI0 I2C.

USI0DR (USI0 Data Register)

USI0SDHR (USI0 SDA Hold Time Register)

USI0SCHR (USI0 SCL High Period Register)

USI0SCLR (USI0 SCL Low Period Register)

USI0SAR (USI0 Slave Address Register)

USI1CR1 (USI1 Control Register 1)

Details USI1CR1 register.

USI1CR2 (USI1 Control Register 2)

Details USI1CR2 register.

USI1CR3 (USI1 Control Register 3)

Details USI1CR3 register.

USI1CR4 (USI1 Control Register 4)

Details USI1CR4 register.

USI1ST1 (USI1 Status Register 1)

Details USI1ST1 register.

USI1ST2 (USI1 Status Register 2)

Details USI1ST2 register.

LCD Driver

Provides an overview of the LCD driver.

LCD Display RAM Organization

LCD Circuit Block Diagram

Shows the block diagram for the LCD driver circuit.

Block Diagram

Shows the block diagram for the LCD driver circuit.

LCDCRH (LCD Driver Control High Register)

LCDCRL (LCD Driver Control Low Register)

LCDCCR (LCD Driver Contrast Control Low Register)

Power Down Operation

IDLE Mode

Describes the IDLE mode operation.

STOP Mode

Describes the STOP mode operation.

Release Operation of STOP Mode

Power Down Operation Register Description

Describes the PCON register.

RESET

Reset Source

Lists the different types of reset sources.

RESET Block Diagram

Shows the block diagram of the reset circuit.

RESET Noise Canceller

Power on RESET

Explains the power-on reset function.

Boot Process Description

External RESETB Input

Describes the external RESETB input.

Brown Out Detector Processor

Explains the brown-out detection circuit.

Block Diagram of BOD

Shows the block diagram of the Brown Out Detector.

Internal Reset at the power fail situation

LVI Block Diagram

Reset Operation Register Description

LVRCR (Low Voltage Reset Control Register)

LVICR (Low Voltage Indicator Control Register)

On-chip Debug System

Two-Pin External Interface

Basic Transmission Packet

Packet Transmission Timing

Start and Stop Condition

Acknowledge Bit

Connection of Transmission

Flash Memory

Overview

Provides an overview of the flash memory.

Description

Flash Program ROM Structure

Register Map

Lists flash memory registers.

Register Description for Flash Memory Control and Status

Register Description for Flash

FMCR (Flash Mode Control Register)

Protection Area (User program mode)

Erase Mode

The Byte erase program procedure in user program mode

Write Mode

The Byte Write program procedure in user program mode

Protection for Invalid Erase/Write

Flow of Protection for Invalid Erase/Write

Read Mode

Code Write Protection Mode

Configure Option

Configure Option Control