ARM ARM7TDMI - Page 30

Open Access
Circuit Descriptions
3-14
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
3.2.8 APB and NISA Bridge
This schematic is shown in A.10 APB and NISA Bridge on page A-11, and shows
the following blocks:
• APB address and data buffers
• APB slave block
• NISA (not-ISA) bus peripherals block
• APB expansion block
• APB and NISA (not-ISA) bridge device
The Advanced Peripheral Bus (APB) connects to the ASB through the address and data
buffers and the bridge which is implemented in (U20). In addition, this bridge generates
signals required to interface to the ISA-type peripherals. This is not a full implementation of
the ISA bus, hence not-ISA (NISA). The NISA bus peripherals comprise the PC card
(PCMCIA) controller and the serial and parallel I/O device.
The bridge chip is responsible for generating all the APB control signals and enabling the
address and data latches. The NISA bus shares the address and data latches with the APB
bus. The bridge detects accesses to APB and NISA address space and acts accordingly.
Link (LK7) is used to select the width of the P_STB signal. The default (link out) is a strobe
of two system clock cycles. If the link is inserted the P_STB signal is asserted for one system
clock cycle only.
Note
The APB peripherals are not guaranteed to function correctly if the link is inserted and the
system clock frequency is above 20MHz. Use this link with care.
3.2.9 NISA Bus Peripherals
The NISA bus peripherals schematic is shown in A.11 NISA Bus Peripherals on page A-12,
and shows the following blocks.
• serial and parallel I/O port block
• PC card (PCMCIA) interface block
Details of these blocks can be found in the following sections.
hrg.book Page 14 Wednesday, July 22, 1998 9:18 AM