Figure 9-17: iMPACT Boundary Scan
7. If the cable is connected correctly, the application will connect and a Xilinx chip
chain will be shown. If the cable is not connected correctly, a cable connection
warning is given.
Figure 9-18: Example Xilinx chip chain
8. The Assign New Configuration File dialog asks you to select an FPGA image
for the first device in the chain or to bypass that device.
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