LX-300
Sanka
Manual
Opamting
Principk
2.3.9 Interface Circuit
Figure 2-20 shows the parallel interface circuit block diagram. Data from the host
mmputer
is
latched within the system
IC
by a WOOSTROBE signal. The system
IC
outputs a BUSY signal
automatically to stop the host computer from sending further data. The CPU block reads the data
latched in the gate array block periodically without generating an interrupt.
STSTEM
IC
PARALLEL l/F
ICI
“w.
y////y/////////
‘ND7-0
--h
5’
STROBE
. . . . .
.
Figure 2-21 shows
EIA-232D.
RXD
is
Figure 2-20. Parallel Interface Block Diagram
the
serial interface circuit block diagram.
The
serial interface conforms to
data received
by
the serial 1/0 of the CPU block from the host commter via
driver/receiver
IC2.
Data is trans%tted to an
irmut
buffer in the svstem
IC
from the
Cl%
block.
Printing starts when a CR code is received or
whe~
the input
but%r
&
filled.
Driver/Reciver
(IC2)
SYSTEM
IC
(ICI)
TXD ●
365
Pm
DTR
PB3
RXD
35‘
Pcl
CTS
6.
~
I
Figure 2-21. Serial Interface Block Diagram
Rev.A
2-17