Model 5601MSC
Model 5601MSC Master SPG/Master Clock System
Page - 30 Revision 2.2 OPERATION
When the 5601MSC is provided with a PAL reference, the AES/DARS outputs can be deterministically
phase aligned. This is because an even number of AES samples are generated during each frame of
the PAL reference. Exactly 1920 AES frames fit into a single PAL frame. The AES/DARS/WC lck menu
item should be set to PAL/integer to assure that the AES/DARS outputs are anchored to the PAL
reference. Because the AES signal coincides with the PAL signal on every frame, the phase of the
AES/DARS outputs will be the same between multiple 5601MSC units that are locked to PAL. In
addition, the AES block length of 192 frames is evenly divisible into a single PAL frame so the start of
an AES block (identified by the Z preamble) will correctly align to line 1 of the PAL reference (as
illustrated in lock diagram #3 of Figure 2-10).
A PAL reference provides enough information for phasing of 50Hz and 25Hz standards, but does not
provide a long enough phase period to deterministically phase 60Hz or 24Hz standards. The standards
that can be phased properly are listed at the bottom of lock diagram #3 (Figure 2-10). The HD
standards listed apply to both the HD test generators and the tri-level sync outputs. The serial digital
video test generator outputs are phased according to SMPTE compliant timing, which may differ from
the timing shown on Tektronix equipment. See the note in section 2.2.6.
If the PAL reference is lost, the unit will freerun on the selected oscillator as described in section 2.2.3.
Note that if the Genlock Range is set to Wide, the freerun drift upon loss of reference will be much
higher. When the PAL reference is regained, the Lock Type menu selection controls how the 5601MSC
will respond to re-align its internal oscillator with the reference (see section 2.2.4).
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