evertz 5601MSC - Automatic Changeover Operation (5601 ACO2); Figure 2-23: Redundant Master Clock;Spg with Auto Changeover System Diagram

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Model 5601MSC

Model 5601MSC Master SPG/Master Clock System

Page - 54 Revision 2.2 OPERATION

2.6. AUTOMATIC CHANGEOVER OPERATION (5601ACO2)

For critical infrastructure requirements a 5601ACO2 can be used to connect two 5601MSC units in a

dual redundant configuration. The 5601ACO2 monitors signal health to decide which of the 5601MSC

units will be connected to the downstream outputs. See the connection diagram below.

Figure 2-23: Redundant Master Clock/SPG with Auto Changeover System Diagram

Main Page

Table of Contents9
Overview17
Figure 1-1: Front View of the 5601MSC17
Quick Start Guide19
Mounting and Power Connections19
Front Panel Installation19
Figure 1-2: 5601MSC with Front Panel Removed and Other Components Partially Extracted19
Configuring the Ethernet Ports20
Selecting and Connecting Frequency References20
Selecting and Connecting Time References21
Checking the Status of the Unit22
Wiring the Outputs22
Figure 1-3: Rear View of 5601MSC22
Configuring the Sync Outputs23
Configuring the Test Generator Outputs23
FTP Feature24
Configuring the Time Outputs24
Figure 1-4: Front Panel Removed, Compactflash Location24
Final Steps of Set up and Securing All Connections25
Access Control25
Theory of Operation27
Figure 2-1: 5601MSC Outputs Block Diagram27
Outputs28
Sync Outputs28
Timecode Outputs (LTC & IRIG)30
Test Generator Options (SDTG, HDTG, 3GTG)31
Global Pedestal Control31
Global Phase Controls31
Table 2-1: Global Phasing Characteristics32
Figure 2-2: IRIG-B127 Format and Alignment to IRIG1 Datum Pulse33
Figure 2-3: 29.97Hz LTC Format and Alignment to NTSC Video33
Figure 2-4: PAL Alignment to 1Hz Pulse and PAL Color Frame Pulse34
Figure 2-5: NTSC Alignment to 1/1.001Hz Pulse and 6/1.001Hz Pulse with VITC Color Framing34
Genlock35
Frequency Locking35
Figure 2-6: Main Oscillator Circuit Block Diagram35
Table 2-2: Frequency Reference Types for the 5601MSC35
Selecting the Frequency Reference Type36
Selecting the Genlock Range36
Lock Type Selection37
Table 2-3: Genlock Range Characteristics37
Video Genlock Operation39
Table 2-4: Supported Analog Video Sync References39
Serial Digital Video Timing40
NTSC Genlock Operation41
Figure 2-7: Lock Diagram #1 - NTSC Reference Without 10Field Reference41
NTSC Genlock with Ten-Field Reference43
Figure 2-8: Lock Diagram #2 - NTSC Reference with Ten-Field Reference43
Figure 2-9: SMPTE ST 318 Ten-Field Reference on NTSC Line 1544
PAL Video Genlock Operation45
Figure 2-10: Lock Diagram #3 - PAL Genlock45
HD Tri-Level Genlock47
Figure 2-11: Lock Diagram #4 - HD Tri-Level Genlock Operation47
Slo-PAL Genlock48
Table 2-5: Phase Locking to HD Tri-Level Standards48
Table 2-6: Slo-PAL Phase Locking48
Continuous Wave and Internal References49
Figure 2-12: Lock Diagram #5 - 10Mhz and Internal Frequency References49
Internal Frequency Reference50
GPS Frequency Reference51
Figure 2-13: Lock Diagram #6 - GPS Frequency Reference51
Timekeeping52
Figure 2-14: Time Locking Block Diagram53
Time Lock Types54
Coordinated Universal Time (UTC)55
Time Reference Sources55
GPS Time Reference56
Modem Time Reference56
Syncro Time Reference57
LTC Time Reference57
VITC Time Reference57
IRIG Time Reference58
SNTP Time Reference58
No Time Reference59
LTC and VITC Timecode59
Figure 2-15: Detail of 29.97Hz LTC Waveform Alignment to NTSC Video59
Dropframe Counting60
Table 2-7: Supported LTC Frame Rates Summary60
Figure 2-16: Dropframe Timecode with Respect to Real-Time over 1-Hour Period61
Figure 2-17: Dropframe Timecode with Respect to Real-Time over a 24-Hour Period61
LTC/VITC Timecode Color Framing62
Figure 2-18: Daily Time Jam Event for 29.97Hz Dropframe Timecode62
Figure 2-19: Dropframe Timecode with Respect to Real-Time over One Week63
IRIG Timecode64
Figure 2-20: Detail of IRIG Alignment to IRIG Datum Pulse64
Table 2-8: Supported IRIG Timecode Formats64
Figure 2-21: IRIG Input and Output Connections65
Network Time Protocol (NTP)66
Figure 2-22: Testing the NTP Server66
Global Positioning System67
Overview67
GPS Lock Operation67
Table 2-9: GPS Status Messages68
GPS Re-Lock in Slow Mode69
GPS Position Insertion into Timecode69
Automatic Changeover Operation (5601ACO2)70
Figure 2-23: Redundant Master Clock/Spg with Auto Changeover System Diagram70
Installation73
Rear Panel73
Reference Loop Connections73
Sync Outputs73
Figure 3-1: 5601MSC Rear Panel73
Ethernet Connections74
Table 3-1: Standard 8-Pin Modular Connector Wiring Color Codes74
Linear Time Code and IRIG Connections75
Table 3-2: LTC out 1 and LTC out 2 XLR Pin Definitions75
Serial Port Connection76
GPS Connection76
Table 3-3: COM Port Pin Definitions76
Table 3-4: GPS Serial Port Pin Definitions76
GPIO Connections (LTC Input, Secondary LTC Outputs, and Syncro Connections)77
Unbalanced Audio Connections77
Table 3-5: GPIO Pin Definitions77
Balanced Audio and Modem Connections78
Table 3-6: AUDIO Removable Terminal Block Pin Definitions78
Test Generator Connections (SDTG, HDTG, 3GTG Options)79
Serial Digital Video Test Generators79
Analog Video Test Generators79
Power Connections79
M4 Grounding Stud80
Mounting and Cooling80
Connecting the General Purpose Inputs and Outputs80
Figure 3-2: Typical GPI Circuitry80
Figure 3-3: Typical GPO Circuitry80
Connecting Two 5601Msc Units in Syncro Mode81
Gps Receiver Installation (Gp Option)81
Mounting the GPS Smart Antenna81
Figure 3-4: Pole Mounting the Smart Antenna82
Connecting the GPS Smart Antenna to the 5601MSC83
Table 3-7: Evertz-Provided GPS Cable (Part WA-T09) Internal Wiring83
System Start-Up84
Table 3-8: Accutime Gold Extender Cable84
How to Operate the Master Clock/Spg85
Front Panel Controls85
Front Panel Buttons85
Figure 4-1: Model 5601MSC Front Panel Layout85
The Status Screens86
Figure 4-2 : Status Screen Highlighting to Indicate Warnings and Faults87
Panel Lock Function92
Front Panel LCD Displays92
Figure 4-3: LCD Displays in Status Screen92
Table 4-1: System Status Messages92
Front Panel Menu System93
Figure 4-4: Menu System and Selection List93
Figure 4-5: Menu Item Live Control93
Figure 4-6: Adjustment Live Control94
Menu Reference Guide95
Table 4-2: Input Menu System Tree95
Table 4-3: Output Menu System Tree101
Table 4-4: General Menu System Tree105
Configuring the Input References106
Selecting the Frequency Reference106
Table 4-5: Root Level of the INPUT Menu106
Configuring the Genlock Capture Range107
Selecting the Frequency Reference Lock Type107
Selecting the Time Reference108
Setting the VITC Reader Line109
Configuring the VITC and LTC Time Reference Date Format109
Selecting the IRIG Input Mode109
Selecting the SNTP IP Enable110
Selecting the SNTP IP Address110
Selecting the Time Reference Lock Type111
Setting the Daily Jam Time for the Time Reference111
Synchronizing the System Oscillator or System Time to the Reference Immediately112
Configuring the Outputs113
Table 4-6: Top Level of the Output Setup Menu113
Configuring the LTC Outputs114
Selecting Normal or Powered LTC 1 Output (LTC1 XLR Output Only)114
Setting the LTC Output Frame Rate and IRIG115
Selecting When the LTC Time Is Synchronized to the System Time116
Synchronizing the LTC Output Time to System Time Immediately116
Synchronizing All the LTC and VITC Outputs to System Time Immediately116
Setting the LTC Frame Offset116
Selecting the LTC Time Zone Offset117
Enabling Daylight Saving Time for the LTC Output117
Setting the LTC/IRIG Output Level117
Enabling LTC Polarity Correction118
Enabling the LTC Output Color Frame Bit118
Selecting the IRIG Output Format118
Setting a Time Offset to the IRIG Output118
Configuring the Sync, 10MHZ and Wordclock Outputs118
Selecting the Standard of the Sync Outputs119
Configuring the VITC Generator for the Color Black Outputs119
Setting the Phase of the Sync Outputs125
Figure 4-7: Video Sync Phase Alignment in 59.94Hz Field Rate Systems125
Figure 4-8: Video Sync Phase Alignment in 50Hz Field Rate Systems125
Configuring the SDI Video Test Generator Outputs (SDTG, HDTG, 3GTG Options)127
Selecting the SDI Test Generator Test Pattern127
Selecting the Interface Type of the SDI Video Test Generator127
Selecting the Image Format of the SDI Video Test Generator128
Selecting Sampling Structure of the SDI Video Test Generator128
Setting the Phase of the SDI Video Test Generator129
Configuring the SDI Test Generator Embedded Audio129
Configuring the On-Screen Message for the SDI Test Generator Outputs131
Configuring the SDI Test Generator Output Drive134
Setting the SDI Test Generator Syncro Mode134
Configuring the Analog Video Test Generator Outputs (SDTG, HDTG, 3GTG Options)134
Selecting the Test Pattern for the Analog Video Test Generator Output134
Selecting the Standard of the Analog Video Test Generator135
Setting the Phase of the Analog Video Test Generator136
Configuring the On-Screen Message of the Analog Video Test Generator137
Setting the Analog Test Generator Syncro Mode140
Test Signals Available141
Signal List for 525, and NTSC141
Signal List for 625, and PAL141
Signal List for HD, 1920X1080141
Additional Test Signals in Compactflash for HD, 1920X1080141
Signal List for HD, 1280X720142
Additional Signals in Compactflash for HD, 1280X720142
Signal List for 2048X1080, 3GB and Dual Link142
Additional Signals in Compactflash for 2048X1080, 3GB and Dual Link142
Configuring the Analog Audio Outputs142
Setting the Analog Audio Tone Frequency143
Configuring the Analog Audio Tone Level143
Setting the Analog Audio Generation Mode143
Configuring the Analog Audio Events144
Configuring the AES and DARS Digital Audio Outputs145
Setting the AES, DARS, and Wordclock Locking Mode145
Setting the Phase of the AES and DARS Outputs146
Setting the Phase of the Wordclock Outputs146
Selecting the Tones to Generate on the AES Digital Audio Outputs147
Setting the Audio Levels for the AES Digital Audio Outputs147
Enabling the Setup Pedestal for All Sync and Analog Test Generator Outputs147
Configuring Global Phase148
Enabling or Disabling the Global Phase Offset148
Entering a Global Phase Offset148
General Configuration Items149
Setting the System Time149
Setting the System Date149
Setting the Leap Seconds149
Table 1-1: Top Level of the General Setup Menu149
Setting the VITC/LTC Userbits150
Setting the VITC/LTC Date Format150
Enabling Syncro Mode151
Setting the GPO 1 and 2 Mode151
Initiating a Firmware Upgrade152
Engineering Menu - Configuring SNMP and Front Panel Menu Access152
Entering the Engineering Menu Password152
Changing the Engineering Menu Password153
Configuring the Simple Network Management Protocol (SNMP)153
Configuring Access to Front Panel Menus157
Setting the Number of Power Supplies Installed159
Resetting the GPS Receiver159
Setting the Daylight Saving Time Rules159
Setting the DST Date Entry Mode161
Setting the DST Start Hour161
Setting the DST Start Day161
Setting the DST Start Week161
Setting the DST Start Month162
Setting the End Hour162
Setting the DST End Day162
Setting the DST End Week162
Setting the DST End Month162
Setting the DST Offset163
Saving and Recalling Presets163
Recalling a User Defined Preset163
Recalling a Factory Preset163
Saving a User Defined Preset164
Configuring the IP Settings for the CONTROL and TIME Ethernet Ports164
Setting up the IP Address for the CONTROL Ethernet Port164
Setting up the Internet Protocol Subnet Mask for the CONTROL Ethernet Port164
Setting up the IP Address for the TIME Ethernet Port164
Setting up the Internet Protocol Subnet Mask for the TIME Ethernet Port165
Setting up the Internet Protocol Gateway Address165
Enabling or Disabling Usage of the Internet Protocol Gateway165
Configuring IP Broadcast Packet Handling165
Configuring the Network Time Protocol Functions (Units Fitted with the T Option)166
Enabling NTP Spoofing166
Configuring the NTP Restrictions167
Configuring the Precision Time Protocol Master168
Master en168
Master Mode168
Setting the PTP DSCP Value169
Setting the Sync Rate169
Setting the Announce Rate169
Setting the Timeout Value169
PTP Priority 1169
PTP Priority 2170
Setting the PTP Domain170
GMP Enable170
Ptp170
Accuracy171
Parts171
Configuring PTP171
Snmp Remote Control with Vistalink173
Updating Vistalink® with a New JAR File173
Figure 4-9: Selecting the Version Information Menu Item174
Figure 4-10: Version Information Dialog174
Applying a JAR Update to the Vistalink® Pro Server175
Figure 4-11: Updating the Vistalink175
Figure 4-12 : Server Restart Warning175
Applying a JAR Update to the Client-Only Version of Vistalink® Pro176
Vistalink® Pro Control Screens for the 5601MSC176
Figure 4-13: Client Notification of JAR Update from Server176
Alarm View Screen177
Figure 4-14: Vistalink Right-Click Pop-Up Menu177
Figure 4-15: Vistalink® Pro Alarm View178
Control View Screens179
Figure 4-16: Vistalink Tabbed Control View179
Table 4-8: Vistalink180
Technical Description181
Specifications181
Analog Sync Outputs181
LTC/IRIG Outputs181
Communications and Control181
Serial Port181
Modem: (M Option Installed)182
Ethernet182
GPS Receiver (GP Option Installed)182
DARS & AES Test Generator Outputs (SDTG, HDTG, or 3GTG Options)183
Reference Loop and Genlock183
Analog Composite Video Test Signal Generators (SDTG, HDTG, or 3GTG Options)184
Analog Audio Tones Generator (SDTG, HDTG, or 3GTG Options)184
SDI Test Generator Outputs (SDTG, HDTG, or 3GTG Options)184
HDTV Test Generator Outputs (HDTG Option Installed)185
3GTV Test Generator Outputs (3GTG Option Installed)186
General Purpose Inputs and Outputs186
Power Supplies187
Compliance187
Mechanical and Environmental187
Ordering Options187
Upgrading the Firmware188
Overview and Setup188
Putting the 5601MSC into Upgrade Mode188
Uploading the Firmware189
Uploading the Firmware Using FTP over Ethernet189
Servicing Instructions and Troubleshooting190
Changing the Fuses190
Replacing the Battery190
Safety Guidelines and Precautions Concerning the Use of 3V Lithium Batteries191
Procedure for Replacing the Battery191
Troubleshooting Issues192
Intermittent Errors on Devices Connected to the SDI Test Generator Outputs (SD/HD/3G)192
GPS Related Issues192
Front Panel Issues193
Vistalink® Pro Issues - SNMP Problems194
Unit Is Not Locking to the Frequency Reference196
Figure 5-1 : Example of the Vistalink(R) Pro Server Sucessfully Binding Port 162196

evertz 5601MSC - Automatic Changeover Operation (5601 ACO2); Figure 2-23: Redundant Master Clock;Spg with Auto Changeover System Diagram

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