X1200 Series Router Manual
Page 7-2
Revision 1.3.2
OUTPUT CONFIGURATIONS
7.2. INPUT SIGNALS ARE WITHIN TIMED TO WITHIN +/- 1 LINE OF REFERENCE.
This example shows the input timing range requirements for a clean switch in the most basic
configuration. The V1 buss output will be delayed 1 line with respect to the reference. A clean switch is
not attainable on the V2 buss output.
SDI
SOURCE
01
SDI
Source
12
Fine Phase = 0
Course Phase = 1
Clean Switch = on
V1
V2
01
12
REF. Black
REF. Black
REF. Black
X1202 SS Router
1 1/2 Line Delay -
1/2 Line Delay -
SDI Signal 1/2 Line.
advanced W.R.T
Ref. Black
SDI signal Held at
1 Line Delayed W.R.T.
Ref. Black
Input Dependant
CleanSwitch
"NOT"
attainable
SDI Signal 1/2 Line
delayed W.R.T
Ref. Black
Figure 7-2: Timing Example 2 – Inputs in Time with Reference
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