evertz X1201S - All Input Signals Are Timed Together but Delayed 5 Lines from Reference

X1200 Series Router Manual
OUTPUT CONFIGURATIONS
Revision 1.3.2
Page 7-3
7.3. ALL INPUT SIGNALS ARE TIMED TOGETHER BUT DELAYED 5 LINES FROM REFERENCE.
This example shows how to set up the router timing when the input signals are delayed by more than one
line. The V1 buss output will be delayed 6 lines with respect to the reference. A clean switch is also
attainable on the V2 buss output.
SDI
SOURCE
01
SDI
Source
12
Fine Phase = 0
Course Phase = 6
Clean Switch = on
V1
V2
01
12
REF. Black
REF. Black
REF. Black
X1202 SS Router
1 Line Delay -
1 Line Delay -
SDI Signals Timed
to 5 lines delayed
Ref. Black
SDI signal Held at
6 Line Delayed W.R.T.
Ref. Black
Input Dependant
CleanSwitch attainable
by setting
Switch Line = 15
Figure 7-3: Timing Example 3 – Inputs in Time but Delayed 5 Lines from Reference