MC68332
USER’S MANUAL
(Continued)
Paragraph Title Page
TABLE OF CONTENTS
7.6.1.3 Emulation Control ......................................................................... 7-13
7.6.1.4 Low-Power Stop Control .............................................................. 7-13
7.6.2 Channel Control Registers ................................................................... 7-14
7.6.2.1 Channel Interrupt Enable and Status Registers ........................... 7-14
7.6.2.2 Channel Function Select Registers .............................................. 7-14
7.6.2.3 Host Sequence Registers ............................................................ 7-14
7.6.2.4 Host Service Registers ................................................................. 7-14
7.6.2.5 Channel Priority Registers ........................................................... 7-14
7.6.3 Development Support and Test Registers ........................................... 7-15
SECTION 8STANDBY RAM WITH TPU EMULATION
8.1 General ........................................................................................................... 8-1
8.2 TPURAM Register Block ................................................................................ 8-1
8.3 TPURAM Array Address Mapping .................................................................. 8-1
8.4 TPURAM Privilege Level ................................................................................ 8-2
8.5 Normal Operation ........................................................................................... 8-2
8.6 Standby Operation ......................................................................................... 8-2
8.7 Low-Power Stop Operation ............................................................................ 8-3
8.8 Reset .............................................................................................................. 8-3
8.9 TPU Microcode Emulation .............................................................................. 8-3
APPENDIX A ELECTRICAL CHARACTERISTICS
APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION
APPENDIX CDEVELOPMENT SUPPORT
C.1 M68MMDS1632 Modular Development System ........................................... C-1
C.2 M68MEVB1632 Modular Evaluation Board ................................................... C-2
APPENDIX D REGISTER SUMMARY
D.1 Central Processing Unit ................................................................................. D-1
D.1.1 CPU32 Register Model .......................................................................... D-2
D.1.2 SR — Status Register ........................................................................... D-3
D.2 System Integration Module ............................................................................ D-3
D.2.1 SIMCR — Module Configuration Register ............................. $YFFA00 D-5
D.2.2 SIMTR — System Integration Test Register .......................... $YFFA02 D-6
D.2.3 SYNCR — Clock Synthesizer Control Register .................... $YFFA04 D-6
D.2.4 RSR — Reset Status Register .............................................. $YFFA07 D-7
D.2.5 SIMTRE — System Integration Test Register (ECLK)........... $YFFA08 D-7
D.2.6 PORTE0/PORTE1 — Port E Data Register.......... $YFFA11, $YFFA13 D-8
Fr
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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