MC68332 QUEUED SERIAL MODULE
USER’S MANUAL 6-19
Delay after transfer can be used to provide a peripheral deselect interval. A delay can
also be inserted between consecutive transfers to allow serial A/D converters to com-
plete conversion. There are two transfer delay options. The user can choose to delay
a standard period after serial transfer is complete or can specify a delay period. Writing
a value to the DTL field in SPCR1 specifies a delay period. The DT bit in command
RAM determines whether the standard delay period (DT = 0) or the specified delay pe-
riod (DT = 1) is used. The following expression is used to calculate the delay:
where DTL equals {1, 2, 3,..., 255}.
A zero value for DTL causes a delay-after-transfer value of 8192/system clock.
Adequate delay between transfers must be specified for long data streams because
the QSPI requires time to load a transmit RAM entry for transfer. Receiving devices
need at least the standard delay between successive transfers. If the system clock is
operating at a slower rate, the delay between transfers must be increased proportion-
ately.
Operation is initiated by setting the SPE bit in SPCR1. Shortly after SPE is set, the
QSPI executes the command at the command RAM address pointed to by NEWQP.
Data at the pointer address in transmit RAM is loaded into the data serializer and
transmitted. Data that is simultaneously received is stored at the pointer address in re-
ceive RAM.
Table 6-3 BITS Encoding
BITS Bits per Transfer
0000 16
0001 Reserved
0010 Reserved
0011 Reserved
0100 Reserved
0101 Reserved
0110 Reserved
0111 Reserved
1000 8
1001 9
1010 10
1011 11
1100 12
1101 13
1110 14
1111 15
Delay after Transfer
32 DTL×
System Clock Frequency
------------------------------------------------------------------=
Standard Delay after Transfer
17
System Clock
------------------------------------=
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Freescale Semiconductor, Inc.
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